公开(公告)号：US07224437B2

公开(公告)日：2007-05-29

申请号：US11141803

申请日：2005-05-31

申请人： Gökhan Perçin ,  Abdurrahman Sezginer ,  Franz Xaver Zach

发明人： Gökhan Perçin ,  Abdurrahman Sezginer ,  Franz Xaver Zach

IPC分类号： G03B27/42 ,  G03B27/52

CPC分类号： G03F7/7025 ,  G03F7/70591

摘要： An apparatus and method for characterizing an illumination pupil of an exposure tool comprises forming a plurality of pinhole test patterns at a plurality of test site locations to facilitate locating test pattern edges for extracting therefrom the illumination pupil characteristics of the exposure tool.

摘要翻译： 用于表征曝光工具的照明光瞳的装置和方法包括在多个测试位置处形成多个针孔测试图案，以便于定位测试图案边缘以从其中提取曝光工具的照明光瞳特性。

公开(公告)号：US07536670B2

公开(公告)日：2009-05-19

申请号：US11141805

申请日：2005-05-31

申请人： Gökhan Perçin ,  Ram Ramanujam ,  Franz Xaver Zach

发明人： Gökhan Perçin ,  Ram Ramanujam ,  Franz Xaver Zach

IPC分类号： G06F17/50

CPC分类号： G03F7/70616 ,  G03F7/705 ,  G03F7/70516

摘要： A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures to be measured and to obtain at least one computational model for optical proximity correction purposes.

摘要翻译： 提供具有验证结构和校准结构的测试掩模，以使得能够在不同剂量和散焦条件下在多个不同测试位置处形成至少一个验证结构的图像和至少一个校准结构，以允许校准结构 以获得用于光学邻近校正目的的至少一个计算模型。

公开(公告)号：US20110154281A1

公开(公告)日：2011-06-23

申请号：US12971845

申请日：2010-12-17

申请人： Franz Xaver Zach

发明人： Franz Xaver Zach

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265 ,  Y10S977/834

摘要： A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.

摘要翻译： 用于校正过程关键布局的装置和方法包括表征一组最坏情况处理变化中的各个对模拟纳米电路布局设计的影响，然后基于这种表征来校正模拟纳米电路布局中的布局几何形状。

公开(公告)号：US07392502B2

公开(公告)日：2008-06-24

申请号：US11169616

申请日：2005-06-30

申请人： Gökhan Percin ,  Ram Ramanujam ,  Franz Xaver Zach ,  Koichi Suzuki

发明人： Gökhan Percin ,  Ram Ramanujam ,  Franz Xaver Zach ,  Koichi Suzuki

IPC分类号： G06F17/50

CPC分类号： G03F1/84 ,  G03F1/36 ,  G03F1/44 ,  G03F7/70441 ,  G03F7/70683

摘要： This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, the model is calibrated using the measurements obtained by running wafers through the same lithography, patterning, and etch processes. In this invention, a novel real time method for verifying and monitoring the calibrated model on a production or monitor wafer is presented: optical proximity corrected (OPC-ed) test and verification structures are placed on scribe lines or cut lines of the production or monitor wafer, and with pre-determined schedule, the critical dimensions and images of these test and verification structures are monitored across wafer and across exposure field.

摘要翻译： 本发明涉及一种用于实时监测和验证生产中的光学邻近校正（OPC）模型和方法的方法。 在对集成电路布局进行OPC之前，应准确准确地描述涉及光刻的光学，物理和化学过程的模型。 通常，使用通过相同的光刻，图案化和蚀刻工艺运行晶片获得的测量来校准模型。 在本发明中，提出了一种用于在生产或监控晶圆上验证和监测校准模型的新型实时方法：将光学邻近校正（OPC-ed）测试和验证结构放置在生产或监视器的划线或切割线上 晶圆，并且具有预定的时间表，这些测试和验证结构的关键尺寸和图像在晶片和曝光场之间进行监控。

公开(公告)号：US08141008B2

公开(公告)日：2012-03-20

申请号：US12971845

申请日：2010-12-17

申请人： Franz Xaver Zach

发明人： Franz Xaver Zach

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265 ,  Y10S977/834

摘要： A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.

摘要翻译： 用于校正过程关键布局的装置和方法包括表征一组最坏情况处理变化中的各个对模拟纳米电路布局设计的影响，然后基于这种表征来校正模拟纳米电路布局中的布局几何形状。

公开(公告)号：US07712069B2

公开(公告)日：2010-05-04

申请号：US11837033

申请日：2007-08-10

申请人： Franz Xaver Zach

发明人： Franz Xaver Zach

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

摘要翻译： 使用基于产量的修改的优点函数提供光学邻近校正方法。 与布局几何相关的已知故障机制用于基于布局特征（例如边缘特征）之间的距离值来导出屈服函数。 在将预测布局图案上的边缘点与设计布局图案上的对应点进行比较时，首先在将预测布局图案上的点移动到较高产量的位置之前进行屈服测试。 如果产量是可接受的，则不再进一步移动。 在达成可接受的收益之前，点的增量移动导致可接受的接近度，该点被标记为进一步考虑。

公开(公告)号：US07882456B2

公开(公告)日：2011-02-01

申请号：US11101872

申请日：2005-04-09

申请人： Franz Xaver Zach

发明人： Franz Xaver Zach

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G03F7/70441 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265 ,  Y10S977/834

摘要： A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.

摘要翻译： 用于校正过程关键布局的装置和方法包括表征一组最坏情况处理变化中的各个对模拟纳米电路布局设计的影响，然后基于这种表征来校正模拟纳米电路布局中的布局几何形状。

公开(公告)号：US20090033353A1

公开(公告)日：2009-02-05

申请号：US12183418

申请日：2008-07-31

申请人： Kaung Shia Yu ,  Franz Xaver Zach

发明人： Kaung Shia Yu ,  Franz Xaver Zach

IPC分类号： G01R31/26 ,  G06F17/50 ,  G03F1/00 ,  H01L23/52

CPC分类号： H01L22/14 ,  G06F17/5068

摘要： Systems and methods for electrical characterization of inter-layer alignment. In one embodiment, a wafer including a plurality of test structures are accessed. The plurality of test structures include chains of conductive segments on multiple layers, coupled by vias. The plurality of test structures are designed with varying amounts of intentional misalignment between the multiple layers. The reactance of each of the plurality of test structures is measured. The reactance is analyzed to determine the process-induced inter-layer misalignment of the integrated circuit wafer.

摘要翻译： 层间对准的电气表征的系统和方法。 在一个实施例中，访问包括多个测试结构的晶片。 多个测试结构包括通过通孔耦合的多层导电段的链。 多个测试结构被设计成在多个层之间具有不同量的有意的不对准。 测量多个测试结构中的每一个的电抗。 分析电抗以确定集成电路晶片的工艺引起的层间未对准。

公开(公告)号：US07861209B2

公开(公告)日：2010-12-28

申请号：US11944769

申请日：2007-11-26

申请人： Franz Xaver Zach

发明人： Franz Xaver Zach

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

公开(公告)号：US07334212B2

公开(公告)日：2008-02-19

申请号：US11221177

申请日：2005-09-07

申请人： Franz Xaver Zach

发明人： Franz Xaver Zach

IPC分类号： G06F15/70

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with the corresponding point on the design layout pattern, a yield test is first undertaken before movement of the points on the predicted layout pattern to a position of higher yield. Where yield is acceptable, no further movement is made. Where incremental movement of points results in coming within acceptable proximity before acceptable yield is reached, the point is flagged for further consideration.

摘要翻译： 使用基于产量的修改的优点函数提供光学邻近校正方法。 与布局几何相关的已知故障机制用于基于布局特征（例如边缘特征）之间的距离值来导出屈服函数。 在将预测布局图案上的边缘点与设计布局图案上的对应点进行比较时，首先在将预测布局图案上的点移动到较高产量的位置之前进行屈服测试。 如果产量是可接受的，则不再进一步移动。 在达成可接受的收益之前，点的增量移动导致可接受的接近度，该点被标记为进一步考虑。