公开(公告)号：US3825995A

公开(公告)日：1974-07-30

申请号：US40120073

申请日：1973-09-27

Applicant: GEN ELECTRIC

Inventor： KURZ B ,  BARRON M ,  BUTLER W

IPC: H01L21/762 ,  H01L27/105 ,  H01L29/00 ,  B01J17/00

CPC classification number: H01L27/1055 ,  H01L21/76202 ,  H01L29/00

Abstract: Undesired coupling of JFET or MESFET bucket-brigade stages through the epitaxial layer in a monolithic integrated bucketbrigade circuit is prevented by isolating adjacent stages by strips of thick oxide dielectric material such as SiO2. The dielectric strips are formed by selective oxidation to obtain local conversion of the n-type silicon epitaxial layer to SiO2. In a second embodiment, elongated spaced-apart mesas of the SiO2 are formed on the substrate prior to forming the patterned n-type silicon epitaxial layer. The storage capacitors of the bucketbrigade stages are MOS devices formed by metal layers overlapping the drain electrode regions of the JFETs or MESFETs diffused in the epitaxial layer with the dielectric material being a SiO2 layer therebetween.

公开(公告)号：US3819954A

公开(公告)日：1974-06-25

申请号：US32864273

申请日：1973-02-01

Applicant: GEN ELECTRIC

Inventor： BUTLER W ,  BARRON M ,  KURZ B

IPC: G11C27/04 ,  H03K25/02

CPC classification number: G11C27/04

Abstract: Compensation for undesired shifts in the D.C. voltage level of a signal being propagated through a charge-transfer delay line is provided by compensating stages spaced at regular intervals along the delay line. The compensating stages are preferably transistors of the same type as that used in the delay line and having their source (or drain) electrodes connected to appropriate nodes along the delay line and their gate electrodes supplied from a pulsed source of voltage having controllable voltage amplitude and pulse repetition rate. The drain (or source) electrodes are grounded for shifting the D.C. voltage level in a first polarity voltage direction and are open or connected to a D.C. voltage source for shifting in the opposite polarity voltage direction.

公开(公告)号：US3784847A

公开(公告)日：1974-01-08

申请号：US3784847D

申请日：1972-10-10

Applicant: GEN ELECTRIC

Inventor： BUTLER W ,  KURZ B ,  BARRON M

IPC: H01L21/762 ,  H01L27/105 ,  H01L29/00 ,  H01L19/00

CPC classification number: H01L27/1055 ,  H01L21/76202 ,  H01L29/00 ,  Y10S148/026 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/05 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/15

Abstract: Undesired coupling of JFET or MESFET bucket-brigade stages through the epitaxial layer in a monolithic integrated bucketbrigade circuit is prevented by isolating adjacent stages by strips of thick oxide dielectric material such as SiO2. The dielectric strips are formed by selective oxidation to obtain local conversion of the n-type silicon epitaxial layer to SiO2. In a second embodiment, elongated spaced-apart mesas of the SiO2 are formed on the substrate prior to forming the patterned n-type silicon epitaxial layer. The storage capacitors of the bucketbrigade stages are MOS devices formed by metal layers overlapping the drain electrode regions of the JFETs or MESFETs diffused in the epitaxial layer with the dielectric material being a SiO2 layer therebetween.

Abstract translation: 通过用SiO 2等厚氧化物电介质材料的条带隔离相邻的级，可以防止JFET或MESFET铲斗级穿越单片式集成斗式电路中的外延层的不期望的耦合。 通过选择性氧化形成介质条，以获得n型硅外延层局部转化为SiO 2。 在第二实施例中，在形成图案化的n型硅外延层之前，在衬底上形成细长的间隔开的SiO 2的台面。 铲斗级的存储电容器是由与外延层中扩散的JFET或MESFET的漏极区域重叠的金属层形成的MOS器件，其间介电材料是SiO 2层。

公开(公告)号：US3825996A

公开(公告)日：1974-07-30

申请号：US40120173

申请日：1973-09-27

Applicant: GEN ELECTRIC

Inventor： BARRON M ,  BUTLER W

IPC: H01L27/105 ,  B01J17/00

CPC classification number: H01L27/1055

Abstract: Undesired coupling of JFET bucket-brigade stages through the epitaxial layer in a monolithic integrated bucket-brigade circuit is prevented by isolation diffusion regions formed in the epitaxial layer along the two sides of a row of bucket-brigade stages. The isolation diffusion regions are slightly spaced from the JFET gate diffused regions and reverse-biased so that depletion regions extend down to the substrate. The close spacing of the gate and isolation diffusion regions results in the gate and isolation depletion regions joining upon application of voltage to the gate to pinch off the transistor. The storage capacitors of the bucket-brigade stages are MOS devices formed by metal layers overlapping the JFET drain electrode regions diffused in the epitaxial layer with the capacitor dielectric being a dielectric layer therebetween.

Abstract translation: 通过沿着一排桶级旅行台的两侧在外延层中形成的隔离扩散区，防止JFET桶级通过外延层在单片集成斗式电路中的不期望的耦合。 隔离扩散区域与JFET栅极扩散区域稍微间隔开并被反向偏置，使得耗尽区域向下延伸到衬底。 栅极和隔离扩散区域的紧密间隔导致栅极和隔离耗尽区域在施加电压到栅极以夹紧晶体管时接合。 斗级级的存储电容器是由在外延层中扩散的JFET漏电极区域重叠的金属层形成的MOS器件，其间的电介质层是电介质层。

公开(公告)号：US3790825A

公开(公告)日：1974-02-05

申请号：US3790825D

申请日：1972-10-10

Applicant: GEN ELECTRIC

Inventor： BARRON M ,  BUTLER W

IPC: H01L27/105 ,  H01L19/00

CPC classification number: H01L27/1055

Abstract: Undesired coupling of JFET bucket-brigade stages through the epitaxial layer in a monolithic integrated bucket-brigade circuit is prevented by isolation diffusion regions formed in the epitaxial layer along the two sides of a row of bucket-brigade stages. The isolation diffusion regions are slightly spaced from the JFET gate diffused regions and are reverse-biased so that depletion regions extend down to the substrate. The close spacing of the gate and isolation diffusion regions results in the gate and isolation depletion regions joining upon application of voltage to the gate to pinch off the transistor. The storage capacitors of the bucket-brigade stages are MOS devices formed by metal layers overlapping the JFET drain electrode regions diffused in the epitaxial layer with the capacitor dielectric being a dielectric layer therebetween.

Abstract translation: 通过沿着一排桶级旅行台的两侧在外延层中形成的隔离扩散区，防止JFET桶级通过外延层在单片集成斗式电路中的不期望的耦合。 隔离扩散区域与JFET栅极扩散区域稍微间隔开并被反向偏置，使得耗尽区域向下延伸到衬底。 栅极和隔离扩散区域的紧密间隔导致栅极和隔离耗尽区域在施加电压到栅极以夹紧晶体管时接合。 斗级级的存储电容器是由在外延层中扩散的JFET漏电极区域重叠的金属层形成的MOS器件，其间的电介质层是电介质层。