公开(公告)号：US3786264A

公开(公告)日：1974-01-15

申请号：US3786264D

申请日：1973-01-02

Applicant: GEN ELECTRIC

Inventor： FERRO A ,  HARNDEN J ,  KURZ B

IPC: H01L27/144 ,  H03K17/79 ,  H01J39/12

CPC classification number: H01L27/1443 ,  H03K17/79 ,  Y10T307/773

Abstract: A light detector amplifier preferably fabricated as a monolithic integrated circuit has high speed of response (in the order of 1 microsecond) at low and high illumination levels, uses low quiescent power and supply voltage, and has an optional thyristor or power transistor output. A transistor preamplifier conducts in the quiescent state and reverse biases a photodiode. Upon illumination, current is diverted to the photodiode and a power amplifier is energized to produce an output which can also provide gating current for a thyristor output. Enhanced performance is obtained by the use of special components, and unique placement of components within the circuit. Voltage excursions are limited in the circuit at several points by current steering, pre-biasing and diode clamping techniques.

Abstract translation: 优选地制造为单片集成电路的光检测放大器在低和高照明水平下具有高响应速度（大约1微秒），使用低静态功率和电源电压，并且具有可选的晶闸管或功率晶体管输出。 晶体管前置放大器处于静态状态，反向偏置光电二极管。 在照明时，电流被转移到光电二极管并且功率放大器通电以产生也可以为晶闸管输出提供门控电流的输出。 通过使用特殊组件，以及电路内元件的独特放置可以获得更强的性能。 通过电流转向，预偏置和二极管钳位技术，电压偏移在几个点处受到限制。

公开(公告)号：US3825995A

公开(公告)日：1974-07-30

申请号：US40120073

申请日：1973-09-27

Applicant: GEN ELECTRIC

Inventor： KURZ B ,  BARRON M ,  BUTLER W

IPC: H01L21/762 ,  H01L27/105 ,  H01L29/00 ,  B01J17/00

CPC classification number: H01L27/1055 ,  H01L21/76202 ,  H01L29/00

Abstract: Undesired coupling of JFET or MESFET bucket-brigade stages through the epitaxial layer in a monolithic integrated bucketbrigade circuit is prevented by isolating adjacent stages by strips of thick oxide dielectric material such as SiO2. The dielectric strips are formed by selective oxidation to obtain local conversion of the n-type silicon epitaxial layer to SiO2. In a second embodiment, elongated spaced-apart mesas of the SiO2 are formed on the substrate prior to forming the patterned n-type silicon epitaxial layer. The storage capacitors of the bucketbrigade stages are MOS devices formed by metal layers overlapping the drain electrode regions of the JFETs or MESFETs diffused in the epitaxial layer with the dielectric material being a SiO2 layer therebetween.

公开(公告)号：US3812518A

公开(公告)日：1974-05-21

申请号：US32058373

申请日：1973-01-02

Applicant: GEN ELECTRIC

Inventor： KURZ B ,  FERRO A

IPC: H01L27/00 ,  H01L31/00 ,  H01L31/10 ,  H01L15/00

CPC classification number: H01L31/00 ,  H01L27/00 ,  H01L31/10

Abstract: A monolithic or discrete photodiode has a patterned region, preferably in the form of elongated strips or fingers, with a spacing less than the diffusion length to obtain low capacitance without loss of photo response. Enhanced efficiency is achieved by the use of surface skin regions and/or a buried layer to confine generated carriers, and by a structure that effects combination of the epitaxial layer-substrate photodiode with the finger photodiode. The low capacitance photodiode is sensitive to visible and infrared light and is useful in high speed circuit applications.

公开(公告)号：US3819954A

公开(公告)日：1974-06-25

申请号：US32864273

申请日：1973-02-01

Applicant: GEN ELECTRIC

Inventor： BUTLER W ,  BARRON M ,  KURZ B

IPC: G11C27/04 ,  H03K25/02

CPC classification number: G11C27/04

Abstract: Compensation for undesired shifts in the D.C. voltage level of a signal being propagated through a charge-transfer delay line is provided by compensating stages spaced at regular intervals along the delay line. The compensating stages are preferably transistors of the same type as that used in the delay line and having their source (or drain) electrodes connected to appropriate nodes along the delay line and their gate electrodes supplied from a pulsed source of voltage having controllable voltage amplitude and pulse repetition rate. The drain (or source) electrodes are grounded for shifting the D.C. voltage level in a first polarity voltage direction and are open or connected to a D.C. voltage source for shifting in the opposite polarity voltage direction.

公开(公告)号：US3784847A

公开(公告)日：1974-01-08

申请号：US3784847D

申请日：1972-10-10

Applicant: GEN ELECTRIC

Inventor： BUTLER W ,  KURZ B ,  BARRON M

IPC: H01L21/762 ,  H01L27/105 ,  H01L29/00 ,  H01L19/00

CPC classification number: H01L27/1055 ,  H01L21/76202 ,  H01L29/00 ,  Y10S148/026 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/05 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/15

Abstract: Undesired coupling of JFET or MESFET bucket-brigade stages through the epitaxial layer in a monolithic integrated bucketbrigade circuit is prevented by isolating adjacent stages by strips of thick oxide dielectric material such as SiO2. The dielectric strips are formed by selective oxidation to obtain local conversion of the n-type silicon epitaxial layer to SiO2. In a second embodiment, elongated spaced-apart mesas of the SiO2 are formed on the substrate prior to forming the patterned n-type silicon epitaxial layer. The storage capacitors of the bucketbrigade stages are MOS devices formed by metal layers overlapping the drain electrode regions of the JFETs or MESFETs diffused in the epitaxial layer with the dielectric material being a SiO2 layer therebetween.

Abstract translation: 通过用SiO 2等厚氧化物电介质材料的条带隔离相邻的级，可以防止JFET或MESFET铲斗级穿越单片式集成斗式电路中的外延层的不期望的耦合。 通过选择性氧化形成介质条，以获得n型硅外延层局部转化为SiO 2。 在第二实施例中，在形成图案化的n型硅外延层之前，在衬底上形成细长的间隔开的SiO 2的台面。 铲斗级的存储电容器是由与外延层中扩散的JFET或MESFET的漏极区域重叠的金属层形成的MOS器件，其间介电材料是SiO 2层。