公开(公告)号：US10892231B2

公开(公告)日：2021-01-12

申请号：US16667376

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

公开(公告)号：US10692737B2

公开(公告)日：2020-06-23

申请号：US16153905

申请日：2018-10-08

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/52 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

Abstract: An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

公开(公告)号：US10332832B2

公开(公告)日：2019-06-25

申请号：US15670423

申请日：2017-08-07

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/495 ,  H01L25/04 ,  H01L23/00 ,  H01L21/48

Abstract: A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.

公开(公告)号：US20140188422A1

公开(公告)日：2014-07-03

申请号：US13731388

申请日：2012-12-31

Applicant: GENERAL ELECTRIC COMPANY

Inventor： William Hullinger Huber ,  Bahman E. Kashef ,  Kaustubh Ravindra Nagarkar

IPC: G01R35/00 ,  G06F17/11

CPC classification number: G01R35/00 ,  A61B5/062 ,  A61B5/6852 ,  A61B2560/0223

Abstract: A position and orientation system and method is provided. A magnetoresistance sensor is provided having a sensor array configured to measure magnetic fields and a metallic coil positioned within the magnetoresistance sensor. In certain embodiments, the magnetic coil may be used to generate a known magnetic field that, when measured by the sensor array, may be used to determine or update a calibration constant for the system.

Abstract translation: 提供了一种位置和方位系统和方法。 提供具有被配置为测量磁场的传感器阵列和位于磁阻传感器内的金属线圈的磁阻传感器。 在某些实施例中，磁线圈可以用于产生已知的磁场，当由传感器阵列测量时可以使用已知的磁场来确定或更新系统的校准常数。

公开(公告)号：US10804116B2

公开(公告)日：2020-10-13

申请号：US16667018

申请日：2019-10-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/28 ,  H01L23/31 ,  H01L23/14 ,  H01L23/00 ,  H01L23/367 ,  H01L27/14 ,  H01L27/146 ,  H01L23/42

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

公开(公告)号：US20200111680A1

公开(公告)日：2020-04-09

申请号：US16153905

申请日：2018-10-08

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L21/48 ,  H01L23/498 ,  H01L25/00 ,  H01L23/538

Abstract: An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

公开(公告)号：US10566301B2

公开(公告)日：2020-02-18

申请号：US15816360

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/50 ,  H01L23/31

Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.

公开(公告)号：US20190254546A1

公开(公告)日：2019-08-22

申请号：US15902841

申请日：2018-02-22

Applicant: General Electric Company

Inventor： Craig Patrick Galligan ,  Nancy Cecelia Stoffel ,  Eric Patrick Davis ,  Kaustubh Ravindra Nagarkar

IPC: A61B5/04 ,  A61B5/00 ,  A61N1/05

Abstract: The present approach relates to the fabrication of probes of a probe array device using wire bonding techniques. In certain implementation, a wire bond apparatus bonds ones end of a wire to a region of a probe array substrate. The second end, however, is not bonded to the substrate and instead is either fabricated to be vertical with respect to the substrate or raised from a non-bonded site to be vertical. The process may be repeated to form multiple probes of the probe array.

公开(公告)号：US20190157226A1

公开(公告)日：2019-05-23

申请号：US15816312

申请日：2017-11-17

Applicant: General Electric Company

Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00

Abstract: A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

公开(公告)号：US20190043802A1

公开(公告)日：2019-02-07

申请号：US15670423

申请日：2017-08-07

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Raymond Albert Fillion ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

IPC: H01L23/522 ,  H01L23/495 ,  H01L25/04 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/82 ,  H01L24/97 ,  H01L25/043 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.