公开(公告)号：US20190326286A1

公开(公告)日：2019-10-24

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US11201152B2

公开(公告)日：2021-12-14

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/51

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US20140282330A1

公开(公告)日：2014-09-18

申请号：US13837763

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Niladri MOJUMDER ,  Bipul Paul ,  Anurag Mittal ,  Juengling Werner

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5072

Abstract: An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices.

Abstract translation: 公开了一种用于方法的方法和相关系统，其使得能够对设备，电路和感兴趣的模块进行优先级排序。 实施例包括：确定指示IC设计的物理布局的电性能的第一电气布局，所述第一电气布局指示所述物理布局的多个设备; 基于所述设备的一个或多个连接来选择所述多个设备的子集; 以及生成指示所述物理布局的电性能的第二电气布局，所述第二电气布局指示所选择的设备，而不包括所述多个设备中的至少一个。