公开(公告)号：US20170345752A1

公开(公告)日：2017-11-30

申请号：US15168899

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/02244 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76864 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53252 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20180040555A1

公开(公告)日：2018-02-08

申请号：US15785665

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L23/528

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20170345766A1

公开(公告)日：2017-11-30

申请号：US15168930

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L21/285

CPC classification number: H01L23/53252 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.

公开(公告)号：US20180144976A1

公开(公告)日：2018-05-24

申请号：US15360255

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng LAW ,  Xunyuan ZHANG ,  Frank W. MONT ,  Genevieve BEIQUE ,  Lei SUN

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76816 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76877 ,  H01L23/5283

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.