公开(公告)号：US20180374759A1

公开(公告)日：2018-12-27

申请号：US15630547

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. HOLT ,  Yi QI ,  Hsien-Ching LO ,  Jianwei PENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.

公开(公告)号：US20190206743A1

公开(公告)日：2019-07-04

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Jianwei PENG ,  Yi QI ,  Hsien-Ching LO ,  Jerome CIAVATTI ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2018 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.