公开(公告)号：US20200144365A1

公开(公告)日：2020-05-07

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. MULFINGER ,  Timothy J. MCARDLE ,  Judson R. HOLT ,  Steffen A. SICHLER ,  Ömür I. AYDIN ,  Wei HONG ,  Yi QI ,  Hui ZANG ,  Liu JIANG

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US20180374759A1

公开(公告)日：2018-12-27

申请号：US15630547

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. HOLT ,  Yi QI ,  Hsien-Ching LO ,  Jianwei PENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.

公开(公告)号：US20210091189A1

公开(公告)日：2021-03-25

申请号：US16823005

申请日：2020-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi LIU ,  Vibhor JAIN ,  Judson R. HOLT ,  Herbert HO ,  Claude ORTOLLAND ,  John J. PEKARIK

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

公开(公告)号：US20210091183A1

公开(公告)日：2021-03-25

申请号：US16830783

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. HOLT ,  Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/16 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

公开(公告)号：US20180233505A1

公开(公告)日：2018-08-16

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. MULFINGER ,  Lakshmanan H. VANAMURTHY ,  Scott BEASOR ,  Timothy J. MCARDLE ,  Judson R. HOLT ,  Hao ZHANG

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

公开(公告)号：US20170294515A1

公开(公告)日：2017-10-12

申请号：US15609295

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy J. MCARDLE ,  Judson R. HOLT ,  Junli WANG

IPC: H01L29/161 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/04 ,  H01L29/045 ,  H01L29/10 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.