公开(公告)号：US20190109197A1

公开(公告)日：2019-04-11

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Wei ZHAO ,  Hui ZANG ,  Hong YU ,  Zhenyu HU ,  Scott BEASOR ,  Erik GEISS ,  Jerome CIAVATTI ,  Jae Gon LEE

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US20160118473A1

公开(公告)日：2016-04-28

申请号：US14525744

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar SINGH ,  Jerome CIAVATTI

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/872

CPC classification number: H01L29/66143 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/872

Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.

Abstract translation: 非平面肖特基二极管包括第一类型的半导体衬底，第一类型包括n型和p型之一。 该结构还包括与耦合到衬底的第一类型相反的第二类型的凸起半导体结构，围绕凸起结构的下部的隔离材料，直立在凸起结构下方的第二类型的第一阱（ s），围绕第一阱的顶部的边缘的第一类型的保护环，在隔离材料上方的凸起结构的顶部上的硅化物的保形层，以及在保形层之上的公共接触 硅化物层。 非平面肖特基二极管可以用非平面晶体管制造，例如FinFET。

公开(公告)号：US20160104774A1

公开(公告)日：2016-04-14

申请号：US14511769

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome CIAVATTI ,  Yanxiang LIU ,  Vara Govindeswara Reddy VAKADA

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1095 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/66545 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7835

Abstract: A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure.

Abstract translation: 非平面横向漂移MOS器件消除了对场板延伸的需要，这减小了栅极宽度。 在一个示例中，凸起结构中的两个源和两个相对较小的栅极允许两个通道和具有镜像流的双电流，每个通道和下游穿过将衬底与漏极区域连接的连接井的中心区域并且向下穿过浅的 包含源极区的阱，然后电流在连接阱的衬底区域内沿相反方向朝着两个漏极行进。 源极和漏极区域可以是分离的凸起结构或连续凸起结构的隔离区域。

公开(公告)号：US20190206743A1

公开(公告)日：2019-07-04

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Jianwei PENG ,  Yi QI ,  Hsien-Ching LO ,  Jerome CIAVATTI ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2018 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US20180374857A1

公开(公告)日：2018-12-27

申请号：US15634227

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Jerome CIAVATTI

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.

公开(公告)号：US20160225895A1

公开(公告)日：2016-08-04

申请号：US14609105

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoli HE ,  Yanxiang LIU ,  Jerome CIAVATTI ,  Myung Hee NAM

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L21/0332 ,  H01L21/32 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7835

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.

Abstract translation: 非平面半导体结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，每个凸起结构中的漏极阱和每个漏极阱中的漏极。 该结构还包括在漏极附近的每个漏极阱中的隔离区域，每个隔离区域到达对应的凸起结构的顶表面，以及每个凸起结构上的导电中心栅极，该导电中心栅极覆盖顶部表面，前部 表面和其后表面，并且覆盖与漏极相对的隔离区域的一部分。 到达凸起结构顶表面的漏极阱中的隔离区域是通过在用HDP氧化物制造期间通过覆盖隔离区域来保护隔离区域的结果，以防止部分去除。