公开(公告)号：US20140017862A1

公开(公告)日：2014-01-16

申请号：US14028957

申请日：2013-09-17

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US08987078B2

公开(公告)日：2015-03-24

申请号：US14028957

申请日：2013-09-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US09293554B2

公开(公告)日：2016-03-22

申请号：US14797982

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg ,  Jian Yu

IPC: H01L21/8238 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L29/456 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.

公开(公告)号：US09337289B2

公开(公告)日：2016-05-10

申请号：US14571628

申请日：2014-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.