公开(公告)号：US20190271918A1

公开(公告)日：2019-09-05

申请号：US15909071

申请日：2018-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Guoxiang Ning ,  Meixiong Zhao ,  Erfeng Ding

IPC: G03F7/20 ,  H01L21/308

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

公开(公告)号：US09425100B1

公开(公告)日：2016-08-23

申请号：US14694276

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhaoxu Shen ,  Min-hwa Chi ,  Haiting Wang ,  Qin Wang ,  Meixiong Zhao ,  Duohui Bei

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L21/823412 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Methods and transistors for circuit structures are provided. The methods include, for instance: defining a channel region in a substrate, the channel region having at least one channel region sidewall adjoining an isolation material; recessing the isolation material to expose an upper portion of the at least one channel region sidewall; and providing a gate structure over a gate interface area with the channel region. The gate interface area includes at least the upper portion of the at least one channel region sidewall and an upper surface of the channel region so that a threshold voltage of the gate structure may be reduced. The methods may also include etching an elongate notch in the upper portion of the at least one channel region sidewall to increase a size of the gate interface area and further reduce the threshold voltage of the gate structure.

Abstract translation: 提供了用于电路结构的方法和晶体管。 所述方法包括例如：在衬底中限定沟道区，所述沟道区具有邻近隔离材料的至少一个沟道区侧壁; 使隔离材料凹陷以暴露至少一个通道区域侧壁的上部; 以及在与沟道区域的栅极接口区域上提供栅极结构。 栅极界面区域至少包括至少一个沟道区域侧壁的上部和沟道区域的上表面，使得可以减小栅极结构的阈值电压。 所述方法还可以包括蚀刻在所述至少一个沟道区域侧壁的上部中的细长凹口以增加栅极界面面积的尺寸并进一步降低栅极结构的阈值电压。

公开(公告)号：US10892222B1

公开(公告)日：2021-01-12

申请号：US16560591

申请日：2019-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erfeng Ding ,  Guoxiang Ning ,  Meixiong Zhao

IPC: H01L23/52 ,  H01L23/525 ,  H01L27/085 ,  H01L23/528 ,  H01L23/522

Abstract: One illustrative IC product disclosed herein includes a first conductive line positioned at a first level within the IC product and a first conductive structure positioned at a second level within the IC product, wherein the second level is lower than the first level. In this illustrative example, the IC product also includes a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance and insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.

公开(公告)号：US10276390B2

公开(公告)日：2019-04-30

申请号：US15097861

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Meixiong Zhao ,  Kuniko Kikuta

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/49 ,  H01L29/40

Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

公开(公告)号：US09379186B1

公开(公告)日：2016-06-28

申请号：US14610140

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qin Wang ,  Min-hwa Chi ,  Meixiong Zhao ,  Zhaoxu Shen ,  Haiting Wang ,  Lucas M. Salazar ,  Lan Yang

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823456 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628

Abstract: Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench.

Abstract translation: 公开了制备具有更长有效栅极长度的CMOS晶体管的方法和所得到的器件。 实施例包括在基板上在其相对侧上形成由间隔物结合的虚拟栅极; 去除伪栅极以在间隔物之间​​形成沟槽; 修改间隔件之间的衬底的栅极通道部分以形成内侧壁或外侧壁; 在修改的栅极沟道部分上沉积保形高k电介质层; 并在沟槽中形成金属栅极。