Integrated circuits with radioactive source material and radiation detection
    1.
    发明授权
    Integrated circuits with radioactive source material and radiation detection 有权
    具有放射源材料和放射线检测的集成电路

    公开(公告)号:US09454886B2

    公开(公告)日:2016-09-27

    申请号:US14037550

    申请日:2013-09-26

    CPC classification number: G08B17/12 G01T7/00 G08B17/11

    Abstract: Radioactive integrated circuit (IC) devices with radioactive material embedded in the substrate of the IC itself, and including logic for “fingerprinting” (that is, determining characteristics that identify the source of the radioactive source material). Radioactive IC devices with embedded detector hardware that determine aspects of radioactivity such as total dose and/or ambient radiation. Radioactive IC devices that can determine an elapsed time based on radioactive decay rates. Radioactive smoke detector using man-made, relatively short half-life radioactive source material.

    Abstract translation: 具有放射性材料的放射性集成电路(IC)装置,其嵌入在IC本身的基板中,并且包括用于“指纹”的逻辑(即,确定识别放射源材料源的特性)。 具有嵌入式检测器硬件的放射性IC器件,其确定放射性的方面,例如总剂量和/或环境辐射。 可以根据放射性衰减率确定经过时间的放射性IC器件。 放射性烟雾探测器采用人造,半衰期较短的放射源材料。

    Method of consumer/producer raw material selection

    公开(公告)号:US09720101B2

    公开(公告)日:2017-08-01

    申请号:US14242283

    申请日:2014-04-01

    CPC classification number: G01T1/178 H01L2924/0002 H01L2924/00

    Abstract: A system, method and computer program product for determining whether a material meets an alpha particle emissivity specification that includes measuring a background alpha particle emissivity for the counter and measuring a combined alpha particle emissivity from the counter containing a sample of the material. The combined alpha particle emissivity includes the background alpha particle emissivity in combination with a sample alpha particle emissivity. The decision statistic is computed based on the observed data and compared to a threshold value. When the decision statistic is less than the threshold value, the material meets the alpha particle emissivity specification. The testing times are computed based on pre-specified criteria so as to meet the needs of both Producer and Consumer.

    Patterning transition metals in integrated circuits
    3.
    发明授权
    Patterning transition metals in integrated circuits 有权
    集成电路中的过渡金属图案化

    公开(公告)号:US09299639B2

    公开(公告)日:2016-03-29

    申请号:US13734524

    申请日:2013-01-04

    Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer line widths, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

    Abstract translation: 集成电路包括多个半导体器件和连接半导体器件的多条导线,其中导线包括沉积在过渡金属上的过渡金属和保护帽。 或者,集成电路包括多个半导体器件和连接半导体器件并具有八十纳米间距的多条导线,其中导电线包括沉积在过渡金属上的过渡金属和保护帽,其中保护性 帽的厚度在约5至15纳米之间。 或者,集成电路包括多个半导体器件和连接半导体器件并具有八十纳米线宽的多条导线,其中导电线包括沉积在过渡金属上的过渡金属和保护帽,其中, 保护帽的厚度介于约5至15纳米之间。

    Patterning transition metals in integrated circuits
    4.
    发明授权
    Patterning transition metals in integrated circuits 有权
    集成电路中的过渡金属图案化

    公开(公告)号:US09299638B2

    公开(公告)日:2016-03-29

    申请号:US13707003

    申请日:2012-12-06

    Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

    Abstract translation: 在集成电路中制造导线包括图案化过渡金属层以形成导电线并且在一个或多个导电线中的至少一些导电线上沉积保护盖。 或者,在集成电路中制造导线包括图案化过渡金属层以形成导电线,其中导线具有八十纳米的间距,并且在至少一些导电线上沉积保护盖,其中, 保护帽的厚度介于约5至15纳米之间。 或者,在集成电路中制造导线包括图案化过渡金属层以形成导电线,其中导线具有八十纳米线宽,并且在至少一些导电线上沉积保护盖,其中 保护帽的厚度在大约5至15纳米之间。

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