公开(公告)号：US20160111374A1

公开(公告)日：2016-04-21

申请号：US14887984

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc. ,  ZEON CORPORATION

Inventor： Markus Brink ,  Robert L. Bruce ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Hiroyuki Miyazoe ,  Masahiro Nakamura

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53295 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

公开(公告)号：US09299639B2

公开(公告)日：2016-03-29

申请号：US13734524

申请日：2013-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Sebastian U. Engelmann ,  Benjamin L. Fletcher ,  Michael S. Gordon ,  Eric A. Joseph

IPC: H01L23/48 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L23/48 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer line widths, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract translation: 集成电路包括多个半导体器件和连接半导体器件的多条导线，其中导线包括沉积在过渡金属上的过渡金属和保护帽。 或者，集成电路包括多个半导体器件和连接半导体器件并具有八十纳米间距的多条导线，其中导电线包括沉积在过渡金属上的过渡金属和保护帽，其中保护性 帽的厚度在约5至15纳米之间。 或者，集成电路包括多个半导体器件和连接半导体器件并具有八十纳米线宽的多条导线，其中导电线包括沉积在过渡金属上的过渡金属和保护帽，其中， 保护帽的厚度介于约5至15纳米之间。

公开(公告)号：US09299638B2

公开(公告)日：2016-03-29

申请号：US13707003

申请日：2012-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cyril Cabral, Jr. ,  Sebastian U. Engelmann ,  Benjamin L. Fletcher ,  Michael S. Gordon ,  Eric A. Joseph

IPC: H01L21/4763 ,  H01L23/48 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L23/48 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract translation: 在集成电路中制造导线包括图案化过渡金属层以形成导电线并且在一个或多个导电线中的至少一些导电线上沉积保护盖。 或者，在集成电路中制造导线包括图案化过渡金属层以形成导电线，其中导线具有八十纳米的间距，并且在至少一些导电线上沉积保护盖，其中， 保护帽的厚度介于约5至15纳米之间。 或者，在集成电路中制造导线包括图案化过渡金属层以形成导电线，其中导线具有八十纳米线宽，并且在至少一些导电线上沉积保护盖，其中 保护帽的厚度在大约5至15纳米之间。

公开(公告)号：US09633948B2

公开(公告)日：2017-04-25

申请号：US14887984

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc. ,  ZEON CORPORATION

Inventor： Markus Brink ,  Robert L. Bruce ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Hiroyuki Miyazoe ,  Masahiro Nakamura

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.

公开(公告)号：US09437443B2

公开(公告)日：2016-09-06

申请号：US13916109

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Markus Brink ,  Michael A. Guillorn ,  Sebastian U. Engelmann ,  Hiroyuki Miyazoe ,  Adam M. Pyzyna ,  Jeffrey W. Sleight

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3088 ,  H01L21/32139

Abstract: A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.

Abstract translation: SIT方法包括以下步骤。 将SIT芯棒材料沉积到衬底上并形成多个SIT芯棒。 间隔物材料被共形沉积到基底上，覆盖每个SIT心轴的顶部和侧面。 原子层沉积（ALD）用于在低温下沉积SIT间隔物。 间隔材料选自金属，金属氧化物，金属氮化物和包括至少一种前述材料的组合。 隔离材料从每个SIT心轴的所有侧面除去，以在每个SIT心轴的侧面上形成SIT侧壁间隔物。 SIT心轴被选择性地移除到SIT侧壁间隔件上，露出SIT侧壁间隔物的图案。 SIT侧壁间隔物的图案被转移到下面的堆叠或衬底。