CAPACITORS POSITIONED AT THE DEVICE LEVEL IN AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF MAKING SUCH CAPACITORS
    3.
    发明申请
    CAPACITORS POSITIONED AT THE DEVICE LEVEL IN AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF MAKING SUCH CAPACITORS 有权
    在集成电路产品中的器件级别定位的电容器和制造这种电容器的方法

    公开(公告)号:US20150123181A1

    公开(公告)日:2015-05-07

    申请号:US14598701

    申请日:2015-01-16

    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.

    Abstract translation: 本文公开的一种说明性的集成电路产品包括位于半导体衬底上方的金属-1金属化层,位于衬底的表面和金属-1金属化层的底部之间的电容器,其中电容器包括多个导电板, 在相对于基板的表面基本正常的方向上定向,以及定位在多个导电板之间的绝缘材料的至少一个区域。

    PARALLEL TEST STRUCTURE
    4.
    发明申请

    公开(公告)号:US20190067056A1

    公开(公告)日:2019-02-28

    申请号:US15682704

    申请日:2017-08-22

    Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

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