PARALLEL TEST STRUCTURE
    5.
    发明申请

    公开(公告)号:US20190067056A1

    公开(公告)日:2019-02-28

    申请号:US15682704

    申请日:2017-08-22

    Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

    ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS
    6.
    发明申请
    ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS 有权
    具有底部连接感应引线的互连模拟电路的电气测试

    公开(公告)号:US20160258998A1

    公开(公告)日:2016-09-08

    申请号:US14635125

    申请日:2015-03-02

    CPC classification number: G01R31/2858 G01N1/00 H01L21/00 H01L2221/00

    Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.

    Abstract translation: 公开了用于电迁移测试的系统。 该系统包括导电构件,在导电构件的顶表面的至少一部分上的绝缘材料的覆盖层,阴极,导电地连接到导电构件的第一端; 导电性地连接到导电构件的第二端的阳极和与阴极和阳极导通地连接的电流源。 沿着导电构件的长度在导电构件的第一端和第二端之间设置多个感应针。 传感针与导电构件的底面导电连接。 至少一个测量装置导电地连接到多个感觉针的至少一个感觉针。 所述至少一个测量装置确定所述导电构件的至少一部分的电阻。

    Integrated circuit (IC) test structure with monitor chain and test wires
    7.
    发明授权
    Integrated circuit (IC) test structure with monitor chain and test wires 有权
    具有监控链和测试线的集成电路(IC)测试结构

    公开(公告)号:US09435852B1

    公开(公告)日:2016-09-06

    申请号:US14862587

    申请日:2015-09-23

    CPC classification number: G01R31/2884 H01L22/34

    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

    Abstract translation: 本公开的方面提供了集成电路(IC)测试结构。 根据本公开的IC结构可以包括:监视器链,其具有通过多个金属线电连接到第二端的第一端,每条金属线位于第一金属层和第二金属层之一内,其中第一金属层 与第二金属层垂直分离; 第一测试线定位在第一金属水平面内并沿第一方向延伸,其中第一测试线与监视器链电绝缘; 以及第二测试线,其位于所述第二金属层内并且在第二方向上延伸,其中所述第二测试线与所述监视器链和所述第一测试线电绝缘,并且其中所述第一方向与所述第二方向不同。

    Integrated circuit structure with continuous metal crack stop

    公开(公告)号:US10109599B2

    公开(公告)日:2018-10-23

    申请号:US15387120

    申请日:2016-12-21

    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

    INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP

    公开(公告)号:US20180174982A1

    公开(公告)日:2018-06-21

    申请号:US15387120

    申请日:2016-12-21

    CPC classification number: H01L23/562 H01L23/5226 H01L23/53257 H01L29/45

    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

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