Abstract:
A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a conventional resistor while spreading generated heat over a larger area. An array of pads and resistive elements can create larger resistances, metal connectors between rows of pads allowing current to flow from a first pad in a first row to a last pad in a last row via pads and resistive elements in each row. Fuses connecting pads in such an array can be included to allow tuning of resistance and/or other electrical properties.
Abstract:
Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.
Abstract:
An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.
Abstract:
An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.
Abstract:
An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.
Abstract:
A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.
Abstract:
Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.
Abstract:
An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.
Abstract:
An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.
Abstract:
An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.