On-chip capacitors with floating islands

    公开(公告)号:US10147783B2

    公开(公告)日:2018-12-04

    申请号:US15463465

    申请日:2017-03-20

    Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

    CMOS INVERTER STRUCTURE AND METHODS OF MAKING SUCH INVERTERS

    公开(公告)号:US20190288690A1

    公开(公告)日:2019-09-19

    申请号:US15922516

    申请日:2018-03-15

    Abstract: One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.

    PARALLEL TEST STRUCTURE
    6.
    发明申请

    公开(公告)号:US20190067056A1

    公开(公告)日:2019-02-28

    申请号:US15682704

    申请日:2017-08-22

    Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

    ON-CHIP CAPACITORS WITH FLOATING ISLANDS
    7.
    发明申请

    公开(公告)号:US20180269275A1

    公开(公告)日:2018-09-20

    申请号:US15463465

    申请日:2017-03-20

    CPC classification number: H01L28/88

    Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

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