公开(公告)号：US20160027775A1

公开(公告)日：2016-01-28

申请号：US14341423

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem AKARVARDAR ,  Ajey P. JACOB ,  Andreas KNORR

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device having Si or high Ge concentration SiGe fins with a narrow width under the gate and a wider width under the spacer and the resulting device are provided. Embodiments include forming fins; forming a dummy gate, with a dummy oxide thereunder and a nitride HM on top, on the fins, the dummy gate formed perpendicular to the fins; forming a nitride spacer on each side of the dummy gate; forming an oxide in-between adjacent gates and planarizing; removing the nitride HM and dummy gate, forming a channel between the nitride spacers; oxidizing the fins in the channel; removing the dummy oxide and oxidized portions of the fins; and forming a RMG on the fins between the nitride spacers.

Abstract translation: 提供了一种形成具有Si或高Ge浓度SiGe鳍的FinFET器件的方法，该栅极在栅极下方具有窄的宽度，并且在间隔物和形成的器件下形成更宽的宽度。 实施例包括形成翅片; 在翅片上形成虚拟栅极，其上具有虚拟氧化物和顶部​​的氮化物HM，垂直于鳍片形成的虚拟栅极; 在所述虚拟栅极的每一侧上形成氮化物间隔物; 在相邻栅极之间形成氧化物并平坦化; 去除氮化物HM和虚拟栅极，在氮化物间隔物之间​​形成通道; 氧化通道中的翅片; 去除虚拟氧化物和翅片的氧化部分; 并在氮化物间隔物之间​​的翅片上形成RMG。

公开(公告)号：US20170256462A1

公开(公告)日：2017-09-07

申请号：US15373852

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Murat Kerem AKARVARDAR ,  Andreas KNORR

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/3083 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/7849

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

公开(公告)号：US20170092764A1

公开(公告)日：2017-03-30

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andre LABONTE ,  Andreas KNORR

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US20160190262A1

公开(公告)日：2016-06-30

申请号：US14676608

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andreas KNORR

IPC: H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate and surrounded at a lower portion thereof by a layer of isolation material, gate structure(s) and confined epitaxial material above active regions of the raised structures, the confined epitaxial material having recessed portion(s) therein. Dummy gate structures surrounding a portion of each of the raised structures are initially used, and the confined epitaxial material is created before replacing the dummy gate structures with final gate structures. The structure further includes silicide on upper surfaces of a top portion of the confined epitaxial material, and contacts above the silicide, the contacts including separate contacts electrically coupled to only one area of confined epitaxial material and common contact(s) electrically coupling two adjacent areas of the confined epitaxial material.

Abstract translation: 非平面半导体结构包括半导体衬底，耦合到衬底的多个凸起的半导体结构，并且在其下部被隔离材料层，栅极结构和凸起结构的有源区上方的限定外延材料包围， 该限制外延材料在其中具有凹入部分。 最初使用围绕每个凸起结构的一部分的虚拟门结构，并且在用最终栅极结构替换伪栅极结构之前产生约束的外延材料。 该结构还包括在限制的外延材料的顶部的上表面上的硅化物和硅化物上方的触点，触点包括电耦合到仅限于一部分的限制性外延材料的单独触点和电耦合两个相邻区域 的限制外延材料。

公开(公告)号：US20140203405A1

公开(公告)日：2014-07-24

申请号：US14220475

申请日：2014-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven R. SOSS ,  Andreas KNORR

IPC: H01L49/02

CPC classification number: H01L28/20

Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

Abstract translation: 形成具有可控电阻的精密电阻器，以补偿随温度发生的变化。 一个实施例包括形成在衬底上具有宽度和长度的电阻半导体元件，跨越电阻半导体元件的宽度图形化导电线，但与之电隔离，并且在电气半导体元件下方形成耗尽沟道 导线来控制电阻半导体元件的电阻值。 该设计能够动态调节电阻，从而提高电阻器的可靠性或允许最终封装期间的电阻修改。