公开(公告)号：US20180197882A1

公开(公告)日：2018-07-12

申请号：US15912141

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David PRITCHARD ,  Lixia LEI ,  Deniz E. CIVAY ,  Scott D. LUNING ,  Neha NAYYAR

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/84 ,  H01L29/40

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/7838

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US20150287604A1

公开(公告)日：2015-10-08

申请号：US14246197

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason E. STEPHENS ,  Lei YUAN ,  Lixia LEI ,  David PRITCHARD ,  Tuhin Guha NEOGI

IPC: H01L21/28

CPC classification number: H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.

Abstract translation: 提供了一种用于在晶片上制造交叉耦合线段以用于例如制造两个或多个晶体管的交叉耦合栅极的方法。 该制造包括：使用第一掩模使具有第一侧面突起的第一线段图案化; 以及使用第二掩模用第二侧面突起构图第二线段。 第二线段与第一线段偏移，并且图案化的第二侧突起覆盖图案化的第一侧突起，并且有助于限定连接第一和第二线段的十字绣线段。 该方法还包括在限定来自第一和第二线段和十字绣段的交叉耦合线段时选择性地切割第一和第二线段。

公开(公告)号：US20200127013A1

公开(公告)日：2020-04-23

申请号：US16168414

申请日：2018-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David PRITCHARD ,  Heng YANG ,  Hongru REN

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/66 ,  H01L21/027 ,  H01L21/762

Abstract: The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.

公开(公告)号：US20150261084A1

公开(公告)日：2015-09-17

申请号：US14205569

申请日：2014-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David PRITCHARD

IPC: G03F1/72

CPC classification number: G03F1/72

Abstract: A method is provided, in which a masking reticle including a plurality of pattern blocks is modified, the modifying including: identifying a first pattern block and a second pattern block of the plurality of pattern blocks where at least a first portion of the first pattern block and a second portion of the second pattern block are in parallel relation; and reducing a length of the first portion of the first pattern block when a transverse separation S between corresponding length edges of the first portion of the first pattern block the second portion of the second pattern block falls within a pre-defined forbidden pitch range for the masking reticle. The method may include repeating the identifying and reducing of pairs of pattern blocks on the mask reticle to remove portions of pattern block pairs spaced apart by a transverse separation falling within a forbidden-pitch range.

Abstract translation: 提供了一种方法，其中修改包括多个图案块的掩蔽掩模版，所述修改包括：识别所述多​​个图案块中的第一图案块和第二图案块，其中所述第一图案块的至少第一部分 并且所述第二图案块的第二部分是平行关系的; 以及当第一图案块的第一部分的相应长度边缘之间的横向间隔S与第二图案块的第二部分之间的横向间隔S落入预定义的禁止间距范围内时，减小第一图案块的第一部分的长度， 掩蔽掩模版。 该方法可以包括重复识别和减少掩模掩模版上的图案块对以去除通过落在禁止间距范围内的横向间隔间隔的图案块对的部分。

公开(公告)号：US20150214064A1

公开(公告)日：2015-07-30

申请号：US14167071

申请日：2014-01-29

Applicant: Globalfoundries Inc.

Inventor： David PRITCHARD ,  Jason E. STEPHENS

IPC: H01L21/308 ,  H01L21/28

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.

Abstract translation: 提供了一种用于制造用于例如在制造两个或更多个晶体管的交叉耦合栅极中的硬掩模使用的交叉耦合线段的方法。 制造结构包括：在基底上提供牺牲心轴，所述牺牲心轴包括穿过所述心轴的横向间隙，将所述牺牲心轴分成第一心轴部分和第二心轴部分; 沿着所述牺牲心轴的侧壁提供侧壁间隔件，其中沿着所述第一心轴部分的侧壁和所述第二心轴部分的侧壁间隔在所述横向间隙内合并形成横杆; 并且移除牺牲心轴并选择性地切割侧壁间隔件以限定来自侧壁间隔件和横杆的交叉耦合线段。 横向间隙可以通过直接打印间隔开的第一和第二心轴部分，或者通过切割牺牲心轴来提供间隙来提供。