公开(公告)号：US10431665B2

公开(公告)日：2019-10-01

申请号：US15875055

申请日：2018-01-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78

摘要： Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US20190355832A1

公开(公告)日：2019-11-21

申请号：US16523340

申请日：2019-07-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088

摘要： One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

公开(公告)号：US09831098B2

公开(公告)日：2017-11-28

申请号：US14797337

申请日：2015-07-13

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC分类号： H01L21/3105 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

摘要： Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

公开(公告)号：US10755918B2

公开(公告)日：2020-08-25

申请号：US16193313

申请日：2018-11-16

申请人： GLOBALFOUNDRIES INC.

发明人： Man Gu ,  Tao Han ,  Charlotte D. Adams

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a spacer with laminate liner and methods of manufacture. The structure includes: a replacement metal gate structure; a laminate low-k liner on the replacement metal gate structure; and a spacer on the laminate low-k liner.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

摘要： In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10192791B1

公开(公告)日：2019-01-29

申请号：US15913547

申请日：2018-03-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Man Gu ,  Tao Han ,  Junsic Hong ,  Jiehui Shu ,  Asli Sirman ,  Charlotte Adams ,  Jinping Liu ,  Keith Tabakman

IPC分类号： H01L21/8242 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092

摘要： A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.

公开(公告)号：US20170018452A1

公开(公告)日：2017-01-19

申请号：US14797337

申请日：2015-07-13

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xinyuan Dou ,  Sukwon Hong ,  Satyajit Shinde ,  Sandeep Gaan ,  Tao Han ,  Carlos Chacon ,  Shimpei Yamaguchi

IPC分类号： H01L21/762 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/423

CPC分类号： H01L21/3105 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/76229 ,  H01L29/42356 ,  H01L29/66795

摘要： Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

摘要翻译： 提供了制造集成电路的方法。 在一个示例中，制造集成电路的方法包括在集成电路基板上的两个鳍结构之间形成隔离沟槽，使用可流动的化学气相沉积工艺在隔离沟槽中形成可流动的膜，并对可流动薄膜进行退火以形成 隔离沟槽中的氧化硅介电层。 使用包括N 2和H 2 O 2的工艺气体在小于约200℃的温度下进行退火。

公开(公告)号：US10777463B2

公开(公告)日：2020-09-15

申请号：US16247761

申请日：2019-01-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Man Gu ,  Tao Han

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

摘要： One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.

公开(公告)号：US20200227320A1

公开(公告)日：2020-07-16

申请号：US16247761

申请日：2019-01-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Man Gu ,  Tao Han

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

摘要： One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

摘要： In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.