公开(公告)号：US09799393B1

公开(公告)日：2017-10-24

申请号：US15169342

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hema Ramamurthy ,  Sanjay Parihar ,  Jongsin Yun

IPC: G11C11/41 ,  G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  H01L27/12

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/1203

Abstract: A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

公开(公告)号：US09293556B2

公开(公告)日：2016-03-22

申请号：US14445893

申请日：2014-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L21/00 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Abstract translation: 本文所述的说明性半导体结构包括包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域的衬底。 逻辑晶体管设置在逻辑晶体管区域。 逻辑晶体管包括栅极电介质和栅电极。 输入/输出晶体管设置在输入/输出晶体管区域。 输入/输出晶体管包括栅极电介质和栅电极。 输入/输出晶体管的栅极电介质具有比逻辑晶体管的栅极电介质更大的厚度。 铁电晶体管设置在铁电晶体管区域。 铁电晶体管包括铁电电介质和栅电极。 铁电电介质布置在铁电晶体管区域和铁电晶体管的栅电极之间。

公开(公告)号：US09536992B2

公开(公告)日：2017-01-03

申请号：US15041581

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/115 ,  H01L21/8238

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括第一晶体管区域和第二晶体管区域上的第一晶体管区域，第二晶体管区域和二氧化硅层。 一层高k电介质材料沉积在二氧化硅层上。 在第二晶体管区域上形成第一金属层。 第一金属层不覆盖第一晶体管区域。 在形成第一金属层之后，在第一晶体管区域和第二晶体管区域上沉积第二金属层。 执行第一退火处理。 第一退火处理从第一晶体管区域上的二氧化硅层的一部分引发第二金属和二氧化硅之间的清除反应。 在退火处理之后，在第一晶体管区域上形成铁电晶体管电介质。

公开(公告)号：US09224455B1

公开(公告)日：2015-12-29

申请号：US14305630

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Seunghwan Seo ,  Jongsin Yun

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C11/40 ,  G11C11/413 ,  G11C11/417

Abstract: A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (SRAM) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor.

Abstract translation: 提供了一种用于在没有较高电源电压的情况下在存储单元中提供附加电流的电路。 实施例包括具有六晶体管静态随机存取存储器（SRAM）单元的电路，所述六晶体管静态随机存取存储器（SRAM）单元包括第一反相器和第二交叉耦合到第二反相器; 第一晶体管，其具有耦合到第一位线的第一源极，耦合到第一反相器的第一漏极和耦合到字线的第一栅极; 第二晶体管，其具有耦合到第二反相器的第二源极，耦合到第二位线的第二漏极和耦合到字线的第二栅极; 以及耦合到第一晶体管和第二晶体管的多个位线感测晶体管。

公开(公告)号：US20180012647A1

公开(公告)日：2018-01-11

申请号：US15711714

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hema Ramamurthy ,  Sanjay Parihar ,  Jongsin Yun

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11 ,  H01L27/12

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/1203

Abstract: At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

公开(公告)号：US20160163821A1

公开(公告)日：2016-06-09

申请号：US15041581

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括第一晶体管区域和第二晶体管区域上的第一晶体管区域，第二晶体管区域和二氧化硅层。 一层高k电介质材料沉积在二氧化硅层上。 在第二晶体管区域上形成第一金属层。 第一金属层不覆盖第一晶体管区域。 在形成第一金属层之后，在第一晶体管区域和第二晶体管区域上沉积第二金属层。 执行第一退火处理。 第一退火处理从第一晶体管区域上的二氧化硅层的一部分引发第二金属和二氧化硅之间的清除反应。 在退火处理之后，在第一晶体管区域上形成铁电晶体管电介质。

公开(公告)号：US20160035856A1

公开(公告)日：2016-02-04

申请号：US14445893

申请日：2014-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf van Bentum ,  Jongsin Yun ,  Seunghwan Seo ,  Joerg Schmid

IPC: H01L29/51 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/6684 ,  H01L21/28158 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517

Abstract: An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

Abstract translation: 本文所述的说明性半导体结构包括包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域的衬底。 逻辑晶体管设置在逻辑晶体管区域。 逻辑晶体管包括栅极电介质和栅电极。 输入/输出晶体管设置在输入/输出晶体管区域。 输入/输出晶体管包括栅极电介质和栅电极。 输入/输出晶体管的栅极电介质具有比逻辑晶体管的栅极电介质更大的厚度。 铁电晶体管设置在铁电晶体管区域。 铁电晶体管包括铁电电介质和栅电极。 铁电电介质布置在铁电晶体管区域和铁电晶体管的栅电极之间。