公开(公告)号：US10217864B2

公开(公告)日：2019-02-26

申请号：US15592444

申请日：2017-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: a bottom source/drain (S/D) region disposed over the substrate, a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion, an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region, a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin. The 1st and 2nd metal gates are electrically isolated from each other by the fin.

公开(公告)号：US20190108873A1

公开(公告)日：2019-04-11

申请号：US15729067

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11 ,  H01L29/78 ,  G11C11/412 ,  H01L21/8238

Abstract: Integrated circuits including a static random access memory (SRAM) cell, methods of operating the same, and methods of fabricating the same are provided herein. In an embodiment, an integrated circuit includes the SRAM cell. The SRAM cell includes a first pass-gate transistor and a second pass-gate transistor. The SRAM cell further includes a first word line and a second word line. The first word line and the second word line are electrically independent of each other. The first pass-gate transistor and/or the second pass-gate transistor include a first gate in electrical communication with the first word line and a second gate in electrical communication with the second word line with the first gate and the second gate included in the same pass-gate transistor.

公开(公告)号：US10147648B1

公开(公告)日：2018-12-04

申请号：US15830217

申请日：2017-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef Watts

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L21/84 ,  H01L29/78

Abstract: A vertical FinFET structure includes a metal layer disposed between adjacent fins of a multi-fin device. The metal layer, which is in electrical contact with a self-aligned work function metal layer, is adapted to decrease the overall resistance of the gate contact for the device. A lower gate contact resistance can improve the reliability and performance of the device, particularly in radio frequency (RF) applications. The metal layer can also extend laterally to provide a contact region for a gate contact.

公开(公告)号：US10177037B2

公开(公告)日：2019-01-08

申请号：US15496429

申请日：2017-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L27/092 ,  H01L25/07 ,  H01L27/108

Abstract: A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.

公开(公告)号：US10026740B1

公开(公告)日：2018-07-17

申请号：US15797533

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Josef Watts

IPC: H01L27/108 ,  H01L29/06

Abstract: One illustrative DRAM structure disclosed herein includes a first memory cell pair, a second memory cell pair, a single diffusion break (SDB) isolation structure positioned between the first and second memory cell pairs, and a single first gate positioned between the first and second memory cell pairs and above the SDB isolation structure.

公开(公告)号：US10593754B2

公开(公告)日：2020-03-17

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L21/265 ,  H01L29/06 ,  H01L21/762

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US09647145B1

公开(公告)日：2017-05-09

申请号：US15012563

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Josef Watts

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L27/0814 ,  H01L27/0629 ,  H01L29/0657 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/8611

Abstract: Diodes for use in FinFET technologies having increased junction electric fields without the need for increased dopant concentrations, as well as methods, apparatus, and systems for fabricating such diodes. The diodes may comprise a semiconductor substrate and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises an N channel doped region comprising an N channel dopant, and the semiconductor substrate further comprises a plurality of P channel doped regions comprising a P channel dopant, wherein each of the P channel doped regions is disposed under one of the plurality of fins and is adjacent to the N channel doped region of the fin.

公开(公告)号：US20200035785A1

公开(公告)日：2020-01-30

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/265

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US09960077B1

公开(公告)日：2018-05-01

申请号：US15679848

申请日：2017-08-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Josef Watts ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088 ,  G03F7/20 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/76264 ,  G03F7/70633 ,  H01L21/02381 ,  H01L21/02496 ,  H01L21/28141 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: Methods of forming a self-aligned CT pillar with the same CD width as the device fins to enable PC isolation and the resulting devices are provided. Embodiments include forming a plurality of fins over a substrate; forming an oxide layer over the substrate and between each fin; removing a portion of a central fin among the plurality, a trench formed in the oxide layer; forming a CT pillar in the trench; recessing the oxide layer below an upper surface of the plurality of fins; forming a gate over the plurality of fins and CT pillar; planarizing the gate down to the CT pillar; and forming a cap layer over the gate and CT pillar.