公开(公告)号：US20190206729A1

公开(公告)日：2019-07-04

申请号：US15860318

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang FANG ,  Shafaat AHMED ,  Zhiguo SUN ,  Jiehui SHU ,  Dinesh R. KOLI ,  Wei-Tsu TSENG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

公开(公告)号：US20160365277A1

公开(公告)日：2016-12-15

申请号：US14740035

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qiang FANG ,  Zhiguo SUN ,  Jiehui SHU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53238

Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.

Abstract translation: 用于电耦合一个或多个下层半导体器件的起始金属化结构，所述结构包括介电材料的底层，其中位于其中的金属填充通孔，底层上的保护层和介电材料的顶层 保护层。 在电介质材料的顶层上形成非晶硅的牺牲层，在牺牲层上方形成保护层，并且通过穿过金属填充的通孔上方的每个层的通孔，以暴露金属 - 通过（s）填充。 然后选择性地去除保护层，以及非晶硅的牺牲层。

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。