公开(公告)号：US20190279860A1

公开(公告)日：2019-09-12

申请号：US15916594

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shariq SIDDIQUI ,  Han YOU ,  Xunyuan ZHANG ,  Rohit GALATAGE ,  Roger A. QUON ,  Christopher J. PENNY

IPC: H01L21/02 ,  H01L49/02 ,  C23C16/455 ,  H01L27/06

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.

公开(公告)号：US20170047404A1

公开(公告)日：2017-02-16

申请号：US14825949

申请日：2015-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven BENTLEY ,  Rohit GALATAGE

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/205

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract translation: 完全III-V半导体或Si基晶体管的源极/漏极包括可以与沟道晶格匹配的底部阻挡层，宽带隙III-V材料的下层和较窄带隙的顶层 III-V材料，下层和顶层之间的组成渐变层从宽带隙材料逐渐过渡到窄带隙材料。

公开(公告)号：US20190115444A1

公开(公告)日：2019-04-18

申请号：US15783270

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven BENTLEY ,  Rohit GALATAGE ,  Puneet Harischandra Suvarna

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L21/28079 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/535 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.