公开(公告)号：US20160379872A1

公开(公告)日：2016-12-29

申请号：US14752210

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal KAMINENI ,  Nicholas Vincent LICAUSI ,  Shariq SIDDIQUI ,  Jeremy Austin WAHL

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/535

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract translation: 一种方法可以包括在半导体结构中形成接触沟槽，使得接触沟槽延伸到接触层，形成包括使用硬掩模层，并用牺牲材料层填充接触沟槽，牺牲材料层形成在触点上 形成。 半导体结构可以包括在接触层上的牺牲材料层。

公开(公告)号：US20160343806A1

公开(公告)日：2016-11-24

申请号：US14718402

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LAM RESEARCH CORPORATION

Inventor： Shariq SIDDIQUI ,  Jody A. FRONHEISER ,  Murat Kerem AKARVARDAR ,  Purushothaman SRINIVASAN ,  Lisa F. EDGE ,  Gangadhara Raja MUTHINTI ,  Georges JACOBI ,  Randolph KNARR

IPC: H01L29/161 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L23/29 ,  H01L23/31 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/161 ,  H01L21/0206 ,  H01L21/02175 ,  H01L21/02236 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/28255 ,  H01L21/31111 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: Methods for fabricating interface passivation layers in a circuit structure are provided. The method includes forming a silicon-germanium layer over a substrate, removing a native oxide layer from an upper surface of the silicon-germanium layer, and exposing the upper surface of the silicon-germanium layer to an ozone-containing solution, resulting in an interface passivation layer with a higher concentration of germanium-dioxide present than germanium-oxide. The resulting interface passivation layer may be part of a gate structure, in which the channel region of the gate structure includes the silicon-germanium layer and the interface passivation layer between the channel region and the dielectric layer of the gate structure has a high concentration of germanium-dioxide.

Abstract translation: 提供了一种在电路结构中制造界面钝化层的方法。 该方法包括在衬底上形成硅锗层，从硅 - 锗层的上表面去除自然氧化物层，并将硅 - 锗层的上表面暴露于含臭氧的溶液中，得到 具有比锗氧化物更高浓度的二氧化锗的界面钝化层。 所得到的界面钝化层可以是栅极结构的一部分，其中栅极结构的沟道区域包括硅 - 锗层，并且沟道区域和栅极结构的电介质层之间的界面钝化层具有高浓度 二氧化锗。

公开(公告)号：US20190279860A1

公开(公告)日：2019-09-12

申请号：US15916594

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shariq SIDDIQUI ,  Han YOU ,  Xunyuan ZHANG ,  Rohit GALATAGE ,  Roger A. QUON ,  Christopher J. PENNY

IPC: H01L21/02 ,  H01L49/02 ,  C23C16/455 ,  H01L27/06

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.