公开(公告)号：US20190067098A1

公开(公告)日：2019-02-28

申请号：US15687591

申请日：2017-08-28

申请人： GLOBALFOUNDRIES INC.

发明人： Aditya Kumar ,  Shiv Kumar Mishra ,  Jean-Baptiste Jacques Laloë ,  Wen Zhi Gao

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L23/532 ,  H01L23/535

摘要： Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a first metal layer contacting a semiconductor substrate in a contact opening; depositing a first nitride barrier layer on the first metal layer; and annealing after depositing the first nitride barrier layer to form silicide region in a junction area underlying the contact opening with the first metal layer and the semiconductor substrate. After the annealing, a second metal layer may be deposited, followed by a second nitride barrier layer. A conductor is formed in a remaining portion of the contact opening. The double barrier layer sets prevent the formation of volcano defects and also advantageously reduce contact resistance.

公开(公告)号：US10453747B2

公开(公告)日：2019-10-22

申请号：US15687591

申请日：2017-08-28

申请人： GLOBALFOUNDRIES INC.

发明人： Aditya Kumar ,  Shiv Kumar Mishra ,  Jean-Baptiste Jacques Laloë ,  Wen Zhi Gao

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L23/532 ,  H01L23/535

摘要： Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a first metal layer contacting a semiconductor substrate in a contact opening; depositing a first nitride barrier layer on the first metal layer; and annealing after depositing the first nitride barrier layer to form silicide region in a junction area underlying the contact opening with the first metal layer and the semiconductor substrate. After the annealing, a second metal layer may be deposited, followed by a second nitride barrier layer. A conductor is formed in a remaining portion of the contact opening. The double barrier layer sets prevent the formation of volcano defects and also advantageously reduce contact resistance.

公开(公告)号：US09419082B2

公开(公告)日：2016-08-16

申请号：US14259726

申请日：2014-04-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Shiv Kumar Mishra ,  Zhiqing Li ,  Scott Beasor ,  Shesh Mani Pandey

IPC分类号： H01L21/22 ,  H01L29/36 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/365 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

摘要： P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

摘要翻译： 提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。 形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加 电影。

公开(公告)号：US20150311085A1

公开(公告)日：2015-10-29

申请号：US14259179

申请日：2014-04-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Eric S. Kozarsky ,  Shiv Kumar Mishra

IPC分类号： H01L21/308 ,  H01L29/06 ,  H01L27/088

CPC分类号： H01L21/3086 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

摘要： Approaches for providing a fin field effect transistor device (FinFET) with a planar block area to enable variable fin pitch and width are disclosed. Specifically, approaches are provided for forming a plurality of fins patterned from a substrate, the plurality of fins comprising: a first set of fins having a variable pitch and a variable width; and a second set of fins having a variable pitch and a uniform width, wherein the first set of fins is adjacent the second set of fins. In one approach, the first set of fins is patterned from the planar block area, which is formed over the substrate, and the second set of fins is formed using a sidewall image transfer (SIT) process.

摘要翻译： 公开了一种用于提供具有平面块区域以实现可变翅片间距和宽度的翅片场效应晶体管器件（FinFET）的方法。 具体地，提供了用于形成从基板图案化的多个翅片的方法，所述多个翅片包括：具有可变间距和可变宽度的第一组翅片; 以及具有可变间距和均匀宽度的第二组翅片，其中所述第一组翅片邻近所述第二组翅片。 在一种方法中，第一组鳍片从形成在衬底上的平面块区域图案化，并且第二组鳍片使用侧壁图像转印（SIT）工艺形成。

公开(公告)号：US10896953B2

公开(公告)日：2021-01-19

申请号：US16382718

申请日：2019-04-12

申请人： GLOBALFOUNDRIES INC.

发明人： Jagar Singh ,  Shiv Kumar Mishra

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L27/06

摘要： The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

公开(公告)号：US20190013397A1

公开(公告)日：2019-01-10

申请号：US15642732

申请日：2017-07-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Jagar Singh ,  Shiv Kumar Mishra

IPC分类号： H01L29/737 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02

摘要： A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.

公开(公告)号：US09236269B2

公开(公告)日：2016-01-12

申请号：US14259179

申请日：2014-04-23

申请人： GLOBALFOUNDRIES Inc.

发明人： Eric S. Kozarsky ,  Shiv Kumar Mishra

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L21/3086 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

摘要： Approaches for providing a fin field effect transistor device (FinFET) with a planar block area to enable variable fin pitch and width are disclosed. Specifically, approaches are provided for forming a plurality of fins patterned from a substrate, the plurality of fins comprising: a first set of fins having a variable pitch and a variable width; and a second set of fins having a variable pitch and a uniform width, wherein the first set of fins is adjacent the second set of fins. In one approach, the first set of fins is patterned from the planar block area, which is formed over the substrate, and the second set of fins is formed using a sidewall image transfer (SIT) process.

摘要翻译： 公开了一种用于提供具有平面块区域以实现可变翅片间距和宽度的翅片场效应晶体管器件（FinFET）的方法。 具体地，提供了用于形成从基板图案化的多个翅片的方法，所述多个翅片包括：具有可变间距和可变宽度的第一组翅片; 以及具有可变间距和均匀宽度的第二组翅片，其中所述第一组翅片邻近所述第二组翅片。 在一种方法中，第一组鳍片从形成在衬底上的平面块区域图案化，并且第二组鳍片使用侧壁图像转印（SIT）工艺形成。

公开(公告)号：US11508810B2

公开(公告)日：2022-11-22

申请号：US17097425

申请日：2020-11-13

申请人： GLOBALFOUNDRIES INC.

发明人： Jagar Singh ,  Shiv Kumar Mishra

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L27/06

摘要： The present disclosure relates to semiconductor structures and, more particularly, to high voltage diode structures and methods of manufacture. The structure includes: a diode structure composed of first well of a first dopant type in a substrate; and a well ring structure of the first dopant type in the substrate which completely surrounds the first well of the first dopant type, and spaced a distance “x” from the first well to cut a leakage path to a shallower second well of a second dopant type.

公开(公告)号：US10236367B2

公开(公告)日：2019-03-19

申请号：US15642732

申请日：2017-07-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Jagar Singh ,  Shiv Kumar Mishra

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266

摘要： A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.

公开(公告)号：US20190013402A1

公开(公告)日：2019-01-10

申请号：US15642675

申请日：2017-07-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Jagar Singh ,  Shiv Kumar Mishra

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06

摘要： A semiconductor device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction between the first and second wells. The second well includes a silicon alloy portion displaced from the PN junction. A source region is positioned in one of the first well or the second well. A drain region is positioned in the other of the first well or the second well. A gate structure is positioned above the substrate laterally positioned between the source region and the drain region.