公开(公告)号：US20140138837A1

公开(公告)日：2014-05-22

申请号：US13682326

申请日：2012-11-20

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC

Inventor： Chengyu Niu ,  Andrew Simon ,  Tibor Bolom

IPC: H01L21/768 ,  H01L23/485

CPC classification number: H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench is opened in a dielectric layer. The trench is then lined with a sandwiched diffusion barrier and metal liner structure and a metal seed layer. The sandwiched diffusion barrier and metal liner structure includes a conformal metal liner layer sandwiched between a first diffusion barrier layer and a second diffusion barrier layer. The metal seed layer is at least lightly doped. The lined trench is then filled by electroplating with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.

Abstract translation: 沟槽在电介质层中打开。 然后将沟槽衬有夹层扩散阻挡层和金属衬垫结构和金属种子层。 夹层扩散阻挡层和金属衬垫结构包括夹在第一扩散阻挡层和第二扩散阻挡层之间的共形金属衬垫层。 金属种子层至少轻掺杂。 然后用金属填充材料电镀填充衬里的沟槽。 然后在金属填充的沟槽上沉积电介质盖层。 掺杂金属种子层的掺杂剂然后迁移到金属填充沟槽和电介质盖层之间的界面，以形成自对准的金属帽。

公开(公告)号：US09559059B2

公开(公告)日：2017-01-31

申请号：US14526678

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/44 ,  H01L23/535 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成开口，从而暴露至少一部分导电接触，执行选择性沉积工艺以在开口中选择性地形成导电材料层 并且在导电接触上，执行退火工艺，在选择性地形成的导电材料层上方沉积至少一种导电材料，以便过度填充该开口，以及执行至少一个平坦化工艺以便去除多余的材料， 导电通孔，其定位在开口中并且导电地耦合到导电接触。

公开(公告)号：US09466530B2

公开(公告)日：2016-10-11

申请号：US14526729

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在至少一层绝缘材料中形成开口，从而暴露至少一部分导电接触，进行选择性金属硅化物形成工艺以选择性地形成金属硅化物层 在所述开口中和在所述导电接触件上，在所述选择性形成的金属硅化物层上方沉积至少一种导电材料，以便过度填充所述开口，并进行至少一个平坦化处理，以便去除多余的材料，从而限定导电通孔 其位于开口中并且导电地耦合到选择性形成的金属硅化物层和导电接触。

公开(公告)号：US20150061135A1

公开(公告)日：2015-03-05

申请号：US14538944

申请日：2014-11-12

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronic Corporation ,  STMICROELECTRONICS, INC.

Inventor： Frieder H. Baumann ,  Tibor Bolom ,  Chao-Kun Hu ,  Koichi Motoyama ,  Chengyu Niu ,  Andrew H. Simon

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

Abstract translation: 具有位于邻近侧壁的扩散阻挡层的结构和在介电材料层中蚀刻的开口的底部。 该结构还具有直接位于扩散阻挡层顶部的金属衬垫，直接位于金属衬垫顶部上的种子层，其中种子层由包括铜的材料制成，铜材料直接位于种子顶部 层，直接位于铜材料的顶部和选择性上的金属盖，以及直接位于金属盖的顶部并且邻近金属盖的封盖层。

公开(公告)号：US20160126190A1

公开(公告)日：2016-05-05

申请号：US14526678

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成开口，从而暴露至少一部分导电接触，执行选择性沉积工艺以在开口中选择性地形成导电材料层 并且在导电接触上，执行退火工艺，在选择性地形成的导电材料层上方沉积至少一种导电材料，以便过度填充该开口，以及执行至少一个平坦化工艺以便去除多余的材料， 导电通孔，其定位在开口中并且导电地耦合到导电接触。

公开(公告)号：US20160126135A1

公开(公告)日：2016-05-05

申请号：US14526729

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在至少一层绝缘材料中形成开口，从而暴露至少一部分导电接触，进行选择性金属硅化物形成工艺以选择性地形成金属硅化物层 在所述开口中和在所述导电接触件上，在所述选择性形成的金属硅化物层上方沉积至少一种导电材料，以便过度填充所述开口，并进行至少一个平坦化处理，以便去除多余的材料，从而限定导电通孔 其位于开口中并且导电地耦合到选择性形成的金属硅化物层和导电接触。

公开(公告)号：US20150325467A1

公开(公告)日：2015-11-12

申请号：US14272787

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Kun Ho Ahn ,  Bernd Hintze ,  Frank Koschinsky

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用原子层沉积（ALD）工艺和物理气相沉积（PVD）工艺在半导体衬底上形成覆盖金属化层的金属线的势垒层。 将衬垫形成材料沉积在阻挡层上方以形成衬垫。 导电金属沉积在衬垫上方。

公开(公告)号：US09177858B1

公开(公告)日：2015-11-03

申请号：US14272787

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Kun Ho Ahn ,  Bernd Hintze ,  Frank Koschinsky

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76862 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用原子层沉积（ALD）工艺和物理气相沉积（PVD）工艺在半导体衬底上形成覆盖金属化层的金属线的势垒层。 将衬垫形成材料沉积在阻挡层上方以形成衬垫。 导电金属沉积在衬垫上方。

公开(公告)号：US09111938B2

公开(公告)日：2015-08-18

申请号：US14538944

申请日：2014-11-12

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronic Corporation ,  STMICROELECTRONICS, INC.

Inventor： Frieder H. Baumann ,  Tibor Bolom ,  Chao-Kun Hu ,  Koichi Motoyama ,  Chengyu Niu ,  Andrew H. Simon

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.