公开(公告)号：US20180374893A1

公开(公告)日：2018-12-27

申请号：US15630534

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Yinjie DING ,  Kangho LEE

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a differential sensing STT MRAM design and the resulting device are provided. Embodiments include rows of programmable cells formed in a magnetoresistive random-access memory (MRAM) device, each row having a source line (SL); and rows of complimentary cells formed in the MRAM device, each row having a SL, wherein a SL of a row of programmable cells and a SL of a row of complimentary cells of a pair of rows form a merged SL.

公开(公告)号：US20180130943A1

公开(公告)日：2018-05-10

申请号：US15803874

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Vinayak Bharat NAIK ,  Kazutaka YAMANE ,  Kangho LEE

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01F41/14 ,  H01F10/32 ,  H01F10/14

CPC classification number: H01L43/08 ,  H01F10/14 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/14 ,  H01F41/302 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunneling junction (MTJ) with a reference layer is less temperature sensitive and is reflow compatible at 260° C. The reference layer may be a composite reference layer having n magnetic layers separated by (n−1) non-magnetic spacer layers. The reference layers may include low temperature coefficient reference layers or a combination of low temperature coefficient and high MR reference layers to produce a low temperature sensitive reference layer with good MR.

公开(公告)号：US20170125664A1

公开(公告)日：2017-05-04

申请号：US15339928

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Taiebeh TAHMASEBI ,  Vinayak Bharat NAIK ,  Kangho LEE ,  Chim Seng SEET ,  Kazutaka YAMANE

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

公开(公告)号：US20170025471A1

公开(公告)日：2017-01-26

申请号：US15080562

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bharat BHUSHAN ,  Juan Boon TAN ,  Wanbing YI ,  Danny Pak-Chum SHUM ,  Shan GAO ,  Kangho LEE

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/12

Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.

Abstract translation: 提出了新兴的存储芯片和形成新兴存储芯片的方法。 例如，公开了磁性随机存取存储器（MRAM）芯片磁屏蔽以及在晶片级处理的形成磁屏蔽的方法。 该方法包括在芯片的前侧，芯片的背面以及在主晶片区域内围绕或邻近磁性隧道结（MTJ）阵列的深沟槽中提供磁屏蔽。 深沟槽中的磁屏蔽连接前侧和后侧磁屏蔽。 该磁屏蔽方法适用于平面和垂直MRAM芯片。 MTJ阵列形成在主晶片区域中，并且在MRAM芯片的后端（BEOL）中的上ILD层的相邻层间电介质层（ILD）层之间形成。

公开(公告)号：US20160260892A1

公开(公告)日：2016-09-08

申请号：US15060647

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Taiebeh TAHMASEBI ,  Kangho LEE ,  Vinayak Bharat NAIK

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack includes a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a first magnesium layer and a synthetic antiferromagnetic (SAF) layer.

Abstract translation: 提出了一种装置和一种形成装置的方法。 提供基板。 基板包括形成在基板表面上的电路部件。 执行后端的处理以在衬底上形成上层间电介质（ILD）层。 上ILD层包括多个ILD水平。 在上ILD层的相邻ILD水平之间形成磁隧道结（MTJ）堆叠。 MTJ堆叠包括自由层，隧道势垒层和固定层。 固定层包括偏振层，包括第一镁层和合成反铁磁（SAF）层的复合纹理断裂层。

公开(公告)号：US20160260891A1

公开(公告)日：2016-09-08

申请号：US15060634

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Taiebeh TAHMASEBI ,  Kangho LEE ,  Vinayak Bharat NAIK

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack comprises a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a ruthenium layer and a synthetic antiferromagnetic (SAF) layer.

Abstract translation: 提出了一种装置和一种形成装置的方法。 提供基板。 基板包括形成在基板表面上的电路部件。 执行后端的处理以在衬底上形成上层间电介质（ILD）层。 上ILD层包括多个ILD水平。 在上ILD层的相邻ILD水平之间形成磁隧道结（MTJ）堆叠。 MTJ堆叠包括自由层，隧道势垒层和固定层。 固定层包括偏振层，包括钌层和合成反铁磁（SAF）层的复合纹理断裂层。

公开(公告)号：US20180123027A1

公开(公告)日：2018-05-03

申请号：US15712109

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kazutaka YAMANE ,  Seungmo NOH ,  Kangho LEE ,  Vinayak Bharat NAIK

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A magnetic tunneling junction (MTJ) with a free layer that is less temperature sensitive and is reflow compatible at 260° C. The magnetic free layer may include various configurations, such as a single as-deposited crystalline magnetic layer or a composite free layer with more than one magnetic layers or a combination of composite and single magnetic layers. The layers of the composite magnetic free layer may include as-deposited crystalline magnetic free layers or a combination of as-deposited crystalline and as-deposited amorphous magnetic layers, with or without a spacer layer. An interface layer may be provided at an interface between the free layer and adjacent layer to apply tensile stress on the free layer in the direction perpendicular to the in-plane direction to enhance perpendicular magnetic anisotropy (PMA) of the free layer.

公开(公告)号：US20160300604A1

公开(公告)日：2016-10-13

申请号：US15095170

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kangho LEE ,  Eng Huat TOH ,  Jack Tim WONG ,  Elgin Kiok Boone QUEK

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  H01L27/228

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device and a method to perform operations of an embedded eFlash device are disclosed. The STT-MRAM device is configured to include an array of STT-MRAM bitcells. The array includes a plurality of bitlines (BLs) and a plurality of word lines (WLs), where the bitlines form columns and the wordlines form rows of STT-MRAM bitcells. Each STT-MRAM bitcell includes a magnetic tunnel junction (MTJ) element coupled in series to an access transistor having a gate terminal and source and drain terminals. The array includes a plurality of source lines (SLs) coupled to the source terminals of the access transistors. A SL of the plurality of SLs is coupled to source terminals of access transistors of two or more adjacent columns of the STT-MRAM cells. The shared SL is parallel to the plurality of BLs. The operations of such a STT-MRAM bitcell are configured to include: an initialization operation, a program operation, and a sector erase operation.

Abstract translation: 公开了一种自旋转移磁力随机存取存储器（STT-MRAM）装置和一种执行嵌入式eFlash装置的操作的方法。 STT-MRAM设备被配置为包括STT-MRAM位单元的阵列。 阵列包括多个位线（BL）和多个字线（WL），其中位线形成列，并且字线形成STT-MRAM位单元的行。 每个STT-MRAM位单元包括与具有栅极端子和源极和漏极端子的存取晶体管串联耦合的磁性隧道结（MTJ）元件。 阵列包括耦合到存取晶体管的源极端子的多个源极线（SL）。 多个SL中的SL耦合到STT-MRAM单元的两个或更多个相邻列的存取晶体管的源极端子。 共享SL与多个BL平行。 这种STT-MRAM位单元的操作被配置为包括：初始化操作，程序操作和扇区擦除操作。

公开(公告)号：US20160276407A1

公开(公告)日：2016-09-22

申请号：US15071180

申请日：2016-03-15

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Vinayak Bharat NAIK ,  Kangho LEE ,  Taiebeh TAHMASEBI ,  Chenchen Jacob WANG

IPC: H01L27/22 ,  H01L43/10 ,  H01L29/66 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/6659 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

Abstract translation: 公开了用于形成半导体器件的半导体器件和方法。 该方法包括形成磁存储单元的存储单元。 形成底部电极和固定层。 固定层包括设置在底部电极上的复合间隔层。 复合间隔层包括基底层和设置在基底层上的非晶缓冲层。 参考层设置在复合间隔层上。 非晶缓冲层用作参考层的模板以具有期望的取向的所需晶体结构。 在固定层上形成至少一个隧道势垒层。 在隧道势垒层之上形成存储层，并且在存储层上形成顶部电极。