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    Image sensor incorporating an array of optically switchable magnetic tunnel junctions
    1.
    发明授权
    Image sensor incorporating an array of optically switchable magnetic tunnel junctions 有权

    公开(公告)号：US11226231B1

    公开(公告)日：2022-01-18

    申请号：US16911950

    申请日：2020-06-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Akhilesh R. Jaiswal ,  Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  David C. Pritchard

    IPC: G01J1/44 ,  H01L43/04 ,  H04N5/374 ,  H04N5/359 ,  H01L43/06 ,  G02F1/19 ,  H01L27/22

    Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

    Circuit structure and method for memory storage with memory cell and MRAM stack
    2.
    发明授权
    Circuit structure and method for memory storage with memory cell and MRAM stack 有权

    公开(公告)号：US11145348B1

    公开(公告)日：2021-10-12

    申请号：US16871129

    申请日：2020-05-11

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Akhilesh R. Jaiswal ,  Ajey Poovannummoottil Jacob ,  Steven R. Soss

    IPC: G11C14/00 ,  G11C11/16 ,  G11C7/10

    Abstract: The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.

    IMAGE SENSOR INCORPORATING AN ARRAY OF OPTICALLY SWITCHABLE MAGNETIC TUNNEL JUNCTIONS
    4.
    发明申请
    IMAGE SENSOR INCORPORATING AN ARRAY OF OPTICALLY SWITCHABLE MAGNETIC TUNNEL JUNCTIONS 有权

    公开(公告)号：US20210404867A1

    公开(公告)日：2021-12-30

    申请号：US16911950

    申请日：2020-06-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Akhilesh R. Jaiswal ,  Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  David C. Pritchard

    IPC: G01J1/44 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H04N5/374 ,  H04N5/359

    Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

    MEMORY WITH A MULTI-INVERTER SENSE CIRCUIT AND METHOD
    6.
    发明申请
    MEMORY WITH A MULTI-INVERTER SENSE CIRCUIT AND METHOD 有权

    公开(公告)号：US20230027460A1

    公开(公告)日：2023-01-26

    申请号：US17380093

    申请日：2021-07-20

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Nishtha Gaul ,  Bipul C. Paul ,  Akhilesh R. Jaiswal

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  H03K19/017

    Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

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