公开(公告)号：US20220221714A1

公开(公告)日：2022-07-14

申请号：US17146509

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Won Suk Lee ,  Thomas G. Weeks, III ,  Michal Rakowski ,  Yusheng Bian ,  Roderick A. Augur ,  Alexander L. Martin ,  Petar I. Todorov

IPC: G02B27/00 ,  G02B6/125

Abstract: Disclosed are a system, method, software tool, etc. for generating a layout indicating the paths for balanced optical waveguides (WGs) of a WG bus. A grid is used to route paths, which extend between corresponding first and second input/output nodes, respectively, and which are within boundaries of a defined area. The paths are automatically rerouted to balance for length and number of bends without overly increasing the lengths of or number of bends in those paths and further without moving the input/output nodes or falling outside the established boundaries. Automatic rerouting of the paths is performed iteratively based on results of various intersection operations related to different path-specific sets of points on the grid to determine when and where to insert additional linear segments and bends into the paths. Then, a layout indicating the balanced paths is generated. Also disclosed is a WG bus structure with balanced optical WGs.

公开(公告)号：US11152496B2

公开(公告)日：2021-10-19

申请号：US16776930

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jagar Singh ,  Alexander L. Martin ,  Alexander M. Derrickson

IPC: H01L29/66 ,  H01L29/02 ,  H01L29/08 ,  H01L29/735 ,  H01L29/737 ,  H01L21/8222 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/285 ,  H01L29/45

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

公开(公告)号：US11575029B2

公开(公告)日：2023-02-07

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L27/082 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/735 ,  H01L29/739 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

公开(公告)号：US20220376093A1

公开(公告)日：2022-11-24

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L29/735 ,  H01L21/84 ,  H01L29/739 ,  H01L29/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/08

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

公开(公告)号：US20230032080A1

公开(公告)日：2023-02-02

申请号：US17388284

申请日：2021-07-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Judson R. Holt ,  Jagar Singh ,  Alexander L. Martin ,  Richard F. Taylor, III

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.

公开(公告)号：US20210242335A1

公开(公告)日：2021-08-05

申请号：US16776930

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander L. Martin ,  Alexander M. Derrickson

IPC: H01L29/735 ,  H01L21/285 ,  H01L29/10 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/266 ,  H01L21/265 ,  H01L29/45 ,  H01L21/3065

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a semiconductor base on a first portion of a raised region of an insulative layer; a first inner emitter/collector (E/C) material on a second portion of the raised region of the insulative layer, wherein the inner E/C material is directly horizontally between the semiconductor base and a sidewall of the raised region; and a first outer E/C material on a first non-raised region of the insulative layer, wherein an upper portion of the first outer E/C material is adjacent the first inner E/C material.

公开(公告)号：US11588044B2

公开(公告)日：2023-02-21

申请号：US17109464

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Richard F. Taylor, III ,  Jagar Singh ,  Alexander L. Martin

IPC: H01L29/739 ,  H03K17/60 ,  H01L29/10 ,  H01L29/06

Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

公开(公告)号：US11500198B2

公开(公告)日：2022-11-15

申请号：US17146509

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Won Suk Lee ,  Thomas G. Weeks, III ,  Michal Rakowski ,  Yusheng Bian ,  Roderick A. Augur ,  Alexander L. Martin ,  Petar I. Todorov

IPC: G02B27/00 ,  G02B6/125

Abstract: Disclosed are a system, method, software tool, etc. for generating a layout indicating the paths for balanced optical waveguides (WGs) of a WG bus. A grid is used to route paths, which extend between corresponding first and second input/output nodes, respectively, and which are within boundaries of a defined area. The paths are automatically rerouted to balance for length and number of bends without overly increasing the lengths of or number of bends in those paths and further without moving the input/output nodes or falling outside the established boundaries. Automatic rerouting of the paths is performed iteratively based on results of various intersection operations related to different path-specific sets of points on the grid to determine when and where to insert additional linear segments and bends into the paths. Then, a layout indicating the balanced paths is generated. Also disclosed is a WG bus structure with balanced optical WGs.

公开(公告)号：US20220173230A1

公开(公告)日：2022-06-02

申请号：US17109464

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Richard F. Taylor, III ,  Jagar Singh ,  Alexander L. Martin

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H03K17/60

Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

公开(公告)号：US11011303B2

公开(公告)日：2021-05-18

申请号：US16106162

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Tung-Hsing Lee ,  Roderick A Augur ,  Siva R K Dangeti ,  Alexander L. Martin ,  Anvitha Shampur

IPC: H01F5/00 ,  H01F27/34 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32

Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.