公开(公告)号：US20240030160A1

公开(公告)日：2024-01-25

申请号：US18479230

申请日：2023-10-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC: H01L23/00 ,  G06F30/392 ,  H01L23/66 ,  H03H1/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/564 ,  G06F30/392 ,  H01L23/66 ,  H03H1/0007 ,  H01L23/585

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US20230032080A1

公开(公告)日：2023-02-02

申请号：US17388284

申请日：2021-07-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Judson R. Holt ,  Jagar Singh ,  Alexander L. Martin ,  Richard F. Taylor, III

IPC: H01L29/735 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.

公开(公告)号：US11990535B2

公开(公告)日：2024-05-21

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/02532 ,  H01L21/2251 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US20230065924A1

公开(公告)日：2023-03-02

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US11588044B2

公开(公告)日：2023-02-21

申请号：US17109464

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Richard F. Taylor, III ,  Jagar Singh ,  Alexander L. Martin

IPC: H01L29/739 ,  H03K17/60 ,  H01L29/10 ,  H01L29/06

Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

公开(公告)号：US20220173230A1

公开(公告)日：2022-06-02

申请号：US17109464

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Alexander M. Derrickson ,  Mankyu Yang ,  Richard F. Taylor, III ,  Jagar Singh ,  Alexander L. Martin

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H03K17/60

Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

公开(公告)号：US11855005B2

公开(公告)日：2023-12-26

申请号：US17352414

申请日：2021-06-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC: G06F30/392 ,  H01L23/66 ,  H03H1/00 ,  H01L23/58 ,  H01L23/00

CPC classification number: H01L23/562 ,  G06F30/392 ,  H01L23/564 ,  H01L23/585 ,  H01L23/66 ,  H03H1/0007

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US11575029B2

公开(公告)日：2023-02-07

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L27/082 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/735 ,  H01L29/739 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

公开(公告)号：US20220406732A1

公开(公告)日：2022-12-22

申请号：US17352414

申请日：2021-06-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H03H1/00 ,  G06F30/392

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US20220376093A1

公开(公告)日：2022-11-24

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L29/735 ,  H01L21/84 ,  H01L29/739 ,  H01L29/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/08

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.