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    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
    1.
    发明公开
    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS 审中-公开

    公开(公告)号：US20230395502A1

    公开(公告)日：2023-12-07

    申请号：US18362044

    申请日：2023-07-31

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/53295 ,  H01L21/76879 ,  H01L21/02164

    Abstract: An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

    Gate contact structure for a transistor device
    2.
    发明授权
    Gate contact structure for a transistor device 有权

    公开(公告)号：US11621333B2

    公开(公告)日：2023-04-04

    申请号：US16555734

    申请日：2019-08-29

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

    IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238

    Abstract: One illustrative transistor device disclosed herein includes, among other things, a gate positioned above a semiconductor substrate, the gate comprising a gate structure, a conductive source/drain metallization structure positioned adjacent the gate, the conductive source/drain metallization structure having a front face, and an insulating spacer that is positioned on and in contact with at least a portion of the front face of the conductive source/drain metallization structure. In this example, the device also includes a gate contact opening that exposes at least a portion of the insulating spacer and a portion of an upper surface of the gate structure and a conductive gate contact structure positioned in the gate contact opening, wherein the conductive gate contact structure contacts at least a portion of the insulating spacer and wherein the conductive gate contact structure is conductively coupled to the gate structure.

    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
    3.
    发明申请
    METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS 有权

    公开(公告)号：US20220108950A1

    公开(公告)日：2022-04-07

    申请号：US17553924

    申请日：2021-12-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

    Metallization lines on integrated circuit products
    7.
    发明授权
    Metallization lines on integrated circuit products 有权

    公开(公告)号：US11233006B2

    公开(公告)日：2022-01-25

    申请号：US16103372

    申请日：2018-08-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

    Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

    Asymmetric gate cut isolation for SRAM
    9.
    发明授权
    Asymmetric gate cut isolation for SRAM 有权

    公开(公告)号：US10950610B2

    公开(公告)日：2021-03-16

    申请号：US16515913

    申请日：2019-07-18

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092

    Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.

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