公开(公告)号：US11614770B2

公开(公告)日：2023-03-28

申请号：US17023145

申请日：2020-09-16

申请人： GOWIN Semiconductor Corporation

发明人： Jianhua Liu ,  Jinghui Zhu ,  Ning Song ,  Tianping Wang ,  Chienkuang Chen ,  Diwakar Chopperla ,  Tianxin Wang ,  Zhenyu Gu ,  Xiaozhi Lin

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/396 ,  G06F30/34 ,  G06F1/08 ,  G06F1/04

摘要： A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

公开(公告)号：US11385709B2

公开(公告)日：2022-07-12

申请号：US17233344

申请日：2021-04-16

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F30/34 ,  G06F1/3246 ,  G06F1/3234

摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

公开(公告)号：US20220027071A1

公开(公告)日：2022-01-27

申请号：US16938771

申请日：2020-07-24

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F3/06 ,  G06F9/4401

摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

公开(公告)号：US20210281264A1

公开(公告)日：2021-09-09

申请号：US17225022

申请日：2021-04-07

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu

IPC分类号： H03K19/1776 ,  G11C13/00 ,  H03K19/17736 ,  G11C16/10 ,  G11C11/22 ,  G11C11/16 ,  H03K19/17724

摘要： A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

公开(公告)号：US10990556B2

公开(公告)日：2021-04-27

申请号：US14831204

申请日：2015-08-20

申请人： Gowin Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu ,  San-Ta Kow

IPC分类号： G06F13/40 ,  G06F13/10 ,  G06F13/16 ,  G06F9/445 ,  G06F15/78 ,  G06F9/4401

摘要： The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

公开(公告)号：US20220294451A1

公开(公告)日：2022-09-15

申请号：US17828037

申请日：2022-05-31

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17736 ,  H03K19/17728

摘要： An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

公开(公告)号：US11368156B2

公开(公告)日：2022-06-21

申请号：US17334985

申请日：2021-05-31

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17736 ,  H03K19/17728

摘要： An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

公开(公告)号：US11309894B2

公开(公告)日：2022-04-19

申请号：US16836899

申请日：2020-03-31

申请人： GOWIN Semiconductor Corporation

发明人： Jinghui Zhu

IPC分类号： H03K19/17728 ,  H03K19/173

摘要： A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.

公开(公告)号：US20210232209A1

公开(公告)日：2021-07-29

申请号：US17233344

申请日：2021-04-16

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu

IPC分类号： G06F1/3296 ,  G06F30/34 ,  G06F1/3246 ,  G06F1/3234

摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

公开(公告)号：US10521150B2

公开(公告)日：2019-12-31

申请号：US16028406

申请日：2018-07-05

申请人： Gowin Semiconductor Corporation

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F3/00 ,  G06F3/06

摘要： The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.