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公开(公告)号：US20240152484A1
公开(公告)日：2024-05-09
申请号：US18414403
申请日：2024-01-16
IPC分类号： G06F13/42 , G06F1/08 , H03K19/17736 , H03M5/04 , H03M9/00
CPC分类号： G06F13/4291 , G06F1/08 , H03K19/17744 , H03M5/04 , H03M9/00 , G06F2213/0042
摘要： A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.
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公开(公告)号：US20240289939A1
公开(公告)日：2024-08-29
申请号：US18642718
申请日：2024-04-22
CPC分类号： G06T7/0004 , G06T1/0007 , G06T7/11 , G06T7/70 , G06V20/36 , H04N7/18 , H04N23/80 , G06T2207/20132 , G06T2207/30164
摘要： An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.
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公开(公告)号：US11474969B1
公开(公告)日：2022-10-18
申请号：US17318841
申请日：2021-05-12
IPC分类号： G06F13/42 , G06F1/08 , H03K19/17736 , H03M9/00 , H03M5/04
摘要： A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.
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公开(公告)号：US20220092398A1
公开(公告)日：2022-03-24
申请号：US17478901
申请日：2021-09-18
摘要： A method and/or apparatus using programmable device for parallel processing logic operations is disclosed. The apparatus, such as a semiconductor integrated circuit die, includes an input memory, a processing unit, and an accelerator. The input memory is used to buffer input signals from an external component. The processing unit, such as a microcontroller, retrieves the input signals from the input memory and generates pre-processed data in accordance with the input signals. The first configured circuit containing configurable logic blocks (“LBs”) of a field programmable logic array (“FPGA”), in one embodiment, is programmed as an accelerator to perform one or more neural networking functions. For example, the accelerator is able to process a set of convolutional operation in response to at least a portion of the pre-processed data offloaded from the processing unit for identifying a result or reference.
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5.发明申请公开(公告)号：US20210376834A1
公开(公告)日：2021-12-02
申请号：US17325025
申请日：2021-05-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/17788 , H03K19/17784 , H03K19/17704 , H03K19/1776
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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公开(公告)号：US11874792B2
公开(公告)日：2024-01-16
申请号：US17968646
申请日：2022-10-18
IPC分类号： G06F13/42 , G06F1/08 , H03K19/17736 , H03M9/00 , H03M5/04
CPC分类号： G06F13/4291 , G06F1/08 , H03K19/17744 , H03M5/04 , H03M9/00 , G06F2213/0042
摘要： A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.
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公开(公告)号：US20230103119A1
公开(公告)日：2023-03-30
申请号：US17489749
申请日：2021-09-29
摘要： An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.
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8.发明申请公开(公告)号：US20220393685A1
公开(公告)日：2022-12-08
申请号：US17891154
申请日：2022-08-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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9.发明授权公开(公告)号：US11496135B2
公开(公告)日：2022-11-08
申请号：US17325025
申请日：2021-05-19
发明人： Grant Thomas Jennings , Jinghui Zhu
IPC分类号： H03K19/177 , H03K19/17788 , H03K19/1776 , H03K19/17704 , H03K19/17784
摘要： A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
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公开(公告)号：US11899608B2
公开(公告)日：2024-02-13
申请号：US17746563
申请日：2022-05-17
CPC分类号： G06F13/4068 , G06F13/385 , G06F13/4027 , G06F13/4291
摘要： A method and/or process of interface bridging device for providing a C physical layer (“C-PHY”) input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.
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