公开(公告)号：US4312068A

公开(公告)日：1982-01-19

申请号：US884465

申请日：1978-03-07

申请人： Gary J. Goss ,  Robert C. Miller

发明人： Gary J. Goss ,  Robert C. Miller

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： H03M13/09

摘要： A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.

摘要翻译： 一种用于确保计算机系统中的任何设备从同一计算机系统中的任何其他设备或另一计算机系统接收的数据的准确性的方法和装置。 每当发送数据单元时，利用计算机系统的现有硬件来生成循环冗余校验字符。 循环冗余校验字符连接在发送的数据的右侧。 每当接收到特定数据时，与生成检查字符相同的方式再次操作检查字符和与其相关联的数据。 如果接收的数据与发送的数据相同，则这种操作的结果为零。

公开(公告)号：US4665482A

公开(公告)日：1987-05-12

申请号：US503963

申请日：1983-06-13

申请人： Thomas L. Murray, Jr. ,  James W. Stonier ,  Gary J. Goss ,  Thomas O. Holtey

发明人： Thomas L. Murray, Jr. ,  James W. Stonier ,  Gary J. Goss ,  Thomas O. Holtey

IPC分类号： G06F13/28 ,  G06F15/167 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F15/167 ,  G06F13/285

摘要： A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller. The CPU then retrieves the address and range information from the mailbox location and initiates a DMC cycle.

摘要翻译： 数据处理系统包括中央处理单元（CPU），输入/输出微处理器，主存储器和多个大容量存储控制器。 在数据多路复用控制（DMC）周期期间，一块信息在大容量存储控制器和主存储器之间传送。 CPU包括存储下一个数据字节被写入或读取的主存储器的地址的寄存器以及指示待传送的数据字节数的范围。 在DMC循环之前，CPU将地址和范围信息存储在I / O RAM中的邮箱位置，I / O微处理器将该信息传输到I / O RAM中的通道表位置。 对于DMC操作，I / O微处理器将地址和范围信息传送到邮箱位置，并将大容量存储信息传输到大容量存储控制器。 它发出CPU中断信号，向大容量存储控制器发出读或写命令。 CPU然后从邮箱位置检索地址和范围信息，并启动DMC循环。

公开(公告)号：US4651329A

公开(公告)日：1987-03-17

申请号：US568933

申请日：1984-01-10

申请人： Gary J. Goss ,  Robert G. H. Moles ,  Randall D. Hinrichs ,  Thomas O. Holtey

发明人： Gary J. Goss ,  Robert G. H. Moles ,  Randall D. Hinrichs ,  Thomas O. Holtey

IPC分类号： H04L1/00 ,  H04L7/033 ,  H04L25/49 ,  H03K9/00

CPC分类号： H04L7/0331 ,  H04L1/0083 ,  H04L25/4925

摘要： An apparatus for decoding data wherein only binary ZEROs are received as electronic pulses, each pulse alternating in opposite directions and wherein binary ONEs require no pulse.The apparatus includes logic for receiving the negative and positive binary ZERO pulses, retiming the pulses and generating a positive pulse for each binary ZERO pulse. The positive pulse is retimed to a pair of complementary pulses and applied to a receiving device, typically a universal synchronous/asynchronous receiver transmitter (USART).

摘要翻译： 一种用于解码数据的装置，其中仅二进制ZERO被接收为电子脉冲，每个脉冲在相反方向上交替，并且其中二进制1不需要脉冲。 该装置包括用于接收负和正二进制ZERO脉冲的逻辑，重新定时脉冲并为每个二进制零脉冲产生正脉冲。 正脉冲重新定时到一对互补脉冲，并施加到接收设备，通常是通用同步/异步接收机发射机（USART）。

公开(公告)号：US4105978A

公开(公告)日：1978-08-08

申请号：US710540

申请日：1976-08-02

申请人： Gary J. Goss ,  Thomas F. Joyce

发明人： Gary J. Goss ,  Thomas F. Joyce

IPC分类号： H03K3/86 ,  G06F1/08 ,  H03K5/04 ,  H03K1/18

CPC分类号： G06F1/08

摘要： A system clock mechanism which can be either stalled (i.e. held indefinitely in a high state) or stretched (i.e. change the rate of pulse occurrence). A first electronic circuit provides pulses having a first predetermined pulse period T.sub.1 with each pulse being generated at a first predetermined rate. A second electronic circuit cooperating with the first electronic circuit modifies the first electronic pulses to generate pulses at a second predetermined rate having a second predetermined pulse period T.sub.2. A third electronic circuit cooperating with the first and second electronic circuits holds the clock circuit indefinitely in a high state.

摘要翻译： 系统时钟机制可以被停滞（即无限期处于高状态）或拉伸（即改变脉冲发生速率）。 第一电子电路提供具有第一预定脉冲周期T1的脉冲，其中每个脉冲以第一预定速率产生。 与第一电子电路协作的第二电子电路修改第一电子脉冲以产生具有第二预定脉冲周期T2的第二预定速率的脉冲。 与第一和第二电子电路协作的第三电子电路将时钟电路无限期地保持在高状态。

公开(公告)号：US4799145A

公开(公告)日：1989-01-17

申请号：US099698

申请日：1987-09-21

申请人： Gary J. Goss ,  Thomas S. Hirsch ,  Thomas O. Holtey

发明人： Gary J. Goss ,  Thomas S. Hirsch ,  Thomas O. Holtey

IPC分类号： G06F9/445 ,  G06F9/46 ,  G06F9/48 ,  G06F15/00 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/4406 ,  G06F9/54

摘要： A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

摘要翻译： 计算机系统包括具有主存储器的第一处理器，具有相关存储器的输入/输出处理器和档案存储器。 在将新的操作系统从归档存储器重新加载到主存储器之前，诸如定时器信息的信息被存储在输入/输出存储器中。 输入/输出存储器继续更新定时器信息，直到第二个操作系统被引导加载到主存储器中。 然后可以将定时器和其他信息返回到第一处理器和主存储器以供第二操作系统使用。

公开(公告)号：US4703322A

公开(公告)日：1987-10-27

申请号：US946663

申请日：1987-01-05

申请人： Gary J. Goss ,  Thomas O. Holtey ,  James C. Siwik

发明人： Gary J. Goss ,  Thomas O. Holtey ,  James C. Siwik

IPC分类号： G09G5/22 ,  G09G1/16

CPC分类号： G09G5/225

摘要： A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.

摘要翻译： 一种可加载字符发生器，其操作可以根据不同的需求进行更改，如外语要求，无需硬件更换和最少的硬件。 字符发生器使用最少的硬件将要显示的字符的字符代码转换为该特定字符的点阵图形。 本发明的可加载字符发生器通过RAM利用2K和8RAM存储器，4K×8存储器，4MUX芯片和具有各种寄存器的Motorola 6845 CRT控制器来代替ROM / PROM，并通过属性缓冲器加载。

公开(公告)号：US4482982A

公开(公告)日：1984-11-13

申请号：US514542

申请日：1983-07-18

申请人： Kin C. Yu ,  Gary J. Goss

发明人： Kin C. Yu ,  Gary J. Goss

IPC分类号： G06F9/48 ,  G06F13/12 ,  G06F13/42 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F9/4825 ,  G06F13/124 ,  G06F13/42 ,  G06F15/167

摘要： A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer, a line microprocessor for communicating with the communication lines and a shared memory, and an I/O microprocessor for communicating with the shared memory and the central processing unit and main memory. The line microprocessor, desiring to communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory with a binary number indicative of the predetermined time delay. The I/O microprocessor adds the output of the free running timer to the binary number, stores the result in a location in a random access memory, and periodically compares the result against the free running timer output. The I/O microprocessor loads a second mailbox with a control character when the results of the comparison indicate that the predetermined time delay is accomplished. The line microprocessor responds to the information in the second mailbox to communicate with the specified communication line.

摘要翻译： 数据处理系统包括中央处理单元，主存储器和服务多个通信线路的通信子系统。 通信子系统包括自由运行定时器，用于与通信线路通信的线路微处理器和共享存储器，以及用于与共享存储器和中央处理单元和主存储器通信的I / O微处理器。 希望在预定时间延迟之后与指定的通信线通信的线路微处理器以指示预定时间延迟的二进制数加载共享存储器中的第一邮箱。 I / O微处理器将自由运行定时器的输出添加到二进制数，将结果存储在随机存取存储器中的一个位置，并定期将结果与自由运行的定时器输出进行比较。 当比较结果指示预定时间延迟完成时，I / O微处理器加载具有控制字符的第二个邮箱。 线路微处理器响应第二个邮箱中的信息与指定的通信线路进行通信。

公开(公告)号：US4665481A

公开(公告)日：1987-05-12

申请号：US503962

申请日：1983-06-13

申请人： James W. Stonier ,  Thomas L. Murray, Jr. ,  Gary J. Goss ,  Thomas O. Holtey

发明人： James W. Stonier ,  Thomas L. Murray, Jr. ,  Gary J. Goss ,  Thomas O. Holtey

IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F13/285

摘要： A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.

摘要翻译： 微程序数据处理系统包括中央处理单元（CPU），主存储器和多个大容量存储控制器。 在数据多路复用控制（DMC）周期期间，一块信息在主存储器和大容量存储控制器之一之间传送。 主存储器在每个字位置存储2个数据字节。 输入/输出RAM存储用于识别大容量存储控制器的通道号信号。 I / O微处理器将I / O RAM寻址到系统总线上的通道号信号，耦合到系统总线的大容量存储控制器响应信道号信号以产生读/写信号。 系统响应请求信号，读/写信号和指示主存储器中寻址位置的左或右位的信号，以产生多个数据请求信号。 响应于数据请求信号寻址只读存储器以读出用于处理数据的多个微程序。

公开(公告)号：US4488231A

公开(公告)日：1984-12-11

申请号：US512701

申请日：1983-07-11

申请人： Kin C. Yu ,  Gary J. Goss

发明人： Kin C. Yu ,  Gary J. Goss

IPC分类号： G06F13/24 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F13/24 ,  G06F15/167

摘要： A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The I/O microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

摘要翻译： 数据处理系统包括具有用于与中央处理单元和主存储器进行通信的I / O微处理器的通信子系统; 以及用于与多个设备通信的线路微处理器。 I / O微处理器和线路微处理器通过存储在共享存储器中的邮箱相互通信。 线路微处理器中断I / O微处理器以处理在主存储器和请求服务的设备之间传输的数据字节，当线路微处理器响应请求设备并加载邮箱时。

公开(公告)号：US4426679A

公开(公告)日：1984-01-17

申请号：US192127

申请日：1980-09-29

申请人： Kin C. Yu ,  Gary J. Goss

发明人： Kin C. Yu ,  Gary J. Goss

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

CPC分类号： G06F13/4226 ,  G06F13/124 ,  G06F13/4022

摘要： A data processing system includes a central processing subsystem, a main memory subsystem, and a number of peripheral subsystems including a communication subsystem all coupled in common to a system bus. Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for an extended period of time, and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle. In order to expediate the response in the case of the transfer over the system bus of an input/output order from the central processing subsystem to the communication subsystem, apparatus in the communication system stores a positive acknowledge or a negative acknowledge signal for each communication channel. The signal is set to indicate a negative acknowledge when the previous input/output order filled the last communication control block. The signal is set to indicate a positive acknowledge when the previous input/output order emptied the communication control block.

摘要翻译： 数据处理系统包括中央处理子系统，主存储器子系统以及包括通用子系统的多个外围子系统，所述通信子系统共同地连接到系统总线。 子系统在异步生成的信息总线传输周期期间相互通信。 每个子系统通过提供三个信号响应中的任何一个来接收信息，包括指示立即响应的肯定确认信号，指示该单元将很可能长时间延长的负确认信号，以及准负值 响应指示在下一个异步生成的总线传输周期期间该单元可能准备就绪。 为了在通过系统总线从中央处理子系统传送到通信子系统的情况下加速响应，通信系统中的装置存储每个通信信道的肯定确认信号或否定确认信号 。 当前一个输入/输出顺序填充最后一个通信控制块时，该信号被设置为指示一个否定确认。 当前一个输入/输出顺序清空通信控制块时，该信号被设置为指示肯定确认。