公开(公告)号：US06380041B1

公开(公告)日：2002-04-30

申请号：US09686476

申请日：2000-10-10

申请人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

发明人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

IPC分类号： H01L21336

CPC分类号： H01L29/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045

摘要： An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

摘要翻译： 具有横向不均匀沟道掺杂分布的超大规模集成电路半导体器件通过以垂直于0°至60°的注入角度使用IV族元件注入来制造，以在掺杂硅衬底中产生间隙 半导体器件的栅极。 在创建间隙之后，使用也与从垂直方向成0°至60°的植入角度植入的III族或V族元件进行沟道掺杂注入。 然后使用快速热退火来通过瞬时增强的扩散将掺杂剂横向驱动到半导体器件的沟道中。

公开(公告)号：US06229177B1

公开(公告)日：2001-05-08

申请号：US09050747

申请日：1998-03-30

申请人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

发明人： Geoffrey Choh-Fei Yeap ,  Ognjen Milic ,  Che-Hoo Ng

IPC分类号： H01L2976

CPC分类号： H01L29/105 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1045

摘要： An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

摘要翻译： 具有横向不均匀沟道掺杂分布的超大规模集成电路半导体器件通过以垂直于0°至60°的注入角度使用IV族元件注入来制造，以在掺杂硅衬底中产生间隙 半导体器件的栅极。 在创建间隙之后，使用也与从垂直方向成0°至60°的植入角度植入的III族或V族元件进行沟道掺杂注入。 然后使用快速热退火来通过瞬时增强的扩散将掺杂剂横向驱动到半导体器件的沟道中。

公开(公告)号：US20130032895A1

公开(公告)日：2013-02-07

申请号：US13195199

申请日：2011-08-01

申请人： Donald R. Disney ,  Ognjen Milic ,  Kun Yi

发明人： Donald R. Disney ,  Ognjen Milic ,  Kun Yi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66659

摘要： A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

摘要翻译： 高压晶体管器件包括在高压晶体管器件的漏极区域和源极区域之间的第一阱区域上的螺旋电阻场板，其中螺旋电阻场板通过第一隔离与第一阱区域分离 并且耦合在漏极区域和源极区域之间。 高压晶体管器件还包括在螺旋电阻场板上的多个第一场板，每个第一场板覆盖螺旋电阻场板的一个或多个段，其中多个第一场板与螺旋电阻隔离 并且其中所述多个第一场板彼此隔离，并且起始第一场板连接到所述源极区域。

公开(公告)号：US20110062489A1

公开(公告)日：2011-03-17

申请号：US12557841

申请日：2009-09-11

申请人： Donald R. Disney ,  Ognjen Milic

发明人： Donald R. Disney ,  Ognjen Milic

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L21/82

CPC分类号： H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66333 ,  H01L29/665 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7395

摘要： An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate and body contact regions by an at least substantially self-aligned silicidation (e.g., salicide) process. The example device may also include one or more sidewall spacers that are each at least substantially aligned between edges of the gate region and the body contact region. The body contact region may also be implanted into the device in at least substantial self-alignment to the sidewall spacer. The method may also include an at least substantially self-aligned silicon etch.

摘要翻译： 公开了一种具有自对准硅化物的改进的功率器件及其制造方法。 示例性功率器件是垂直功率器件，其包括通过至少基本上自对准的硅化（例如自对准硅）工艺在栅极和体接触区域上形成的触点。 示例性装置还可以包括一个或多个侧壁间隔件，每个侧壁间隔件至少基本上对准在栅极区域和主体接触区域的边缘之间。 身体接触区域也可以以至少基本上与对侧隔离物自对准的方式植入到装置中。 该方法还可以包括至少基本上自对准的硅蚀刻。

公开(公告)号：US20100302810A1

公开(公告)日：2010-12-02

申请号：US12474037

申请日：2009-05-28

申请人： Michael R. Hsing ,  Ognjen Milic ,  Tiesheng Li

发明人： Michael R. Hsing ,  Ognjen Milic ,  Tiesheng Li

IPC分类号： H02M3/335 ,  H01L27/085 ,  H01L21/337 ,  H01L21/336

CPC分类号： H02M1/36 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/7803 ,  H01L29/7828 ,  H01L29/8083 ,  H02M3/33523 ,  H02M2001/0006

摘要： Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.

摘要翻译： 具有集成的低功率漏电装置和相关方法的电压转换器在本文中公开。 在一个实施例中，电压转换器包括被配置为将第一电信号转换成不同于第一电信号的第二电信号的开关。 电压转换器还包括可操作地耦合到开关的控制器和电耦合到控制器的漏电装置。 控制器被配置为控制开关的导通和截止门，并且漏电装置被配置为向控制器输送电力。 漏电装置和开关形成在第一半导体衬底上，并且控制器形成在与第一半导体衬底分离的第二半导体衬底上。

公开(公告)号：US06320236B1

公开(公告)日：2001-11-20

申请号：US09413737

申请日：1999-10-06

申请人： Zoran Krivokapic ,  Ognjen Milic

发明人： Zoran Krivokapic ,  Ognjen Milic

IPC分类号： H01L2976

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/823412

摘要： An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack. Adjacent gate stacks can have asymmetric channels with the same dopant concentration, or may be fabricated having different concentrations by varying the height of the photoresist mask to achieve a wider ion-implantation beam and thus form a higher dopant concentration on the target channel region. The optimized gates with higher dopant concentration improves off-state leakage current (10−8 amps/micron), but reduce the gate speed. The gates may also be optimized for gate speed and power consumption by producing uniformly doped asymmetric gates (20-50 pico-second fall time delays being achievable).

摘要翻译： 公开了一种具有优化的非对称沟道区域的集成半导体逻辑门装置及其制造方法。 制造工艺包括离子注入通道的漏极侧，通过使用十字交叉形式的离子注入在栅极晶体管上产生非对称沟道。 十字交叉离子注入在形成多个栅极堆叠之后进行，并且通过图案化的光致抗蚀剂掩模来实现，该图案化的光刻胶掩模在相邻的栅极堆叠之上留下开放的未受保护的区域，通过其进行离子注入。 十字交叉离子注入包括由影响光致抗蚀剂掩模的高度的切线确定的两个倾斜角，栅极堆叠对上的未保护开口的宽度和沟道区域的宽度，包括与 源极/漏极势垒在覆盖栅极堆叠下方最小的点。 相邻的栅极堆叠可以具有相同的掺杂剂浓度的不对称沟道，或者可以通过改变光致抗蚀剂掩模的高度来制造具有不同的浓度，以实现较宽的离子注入束并因此在目标沟道区上形成更高的掺杂剂浓度。 具有较高掺杂浓度的优化栅极可提高截止状态下的漏电流（10-8安培/微米），但降低栅极速度。 也可以通过产生均匀掺杂的非对称栅极（20-50微微秒的下降时间延迟可实现）来对栅极速度和功耗进行优化。

公开(公告)号：US06246096B1

公开(公告)日：2001-06-12

申请号：US09103388

申请日：1998-06-24

申请人： Zoran Krivokapic ,  Ognjen Milic

发明人： Zoran Krivokapic ,  Ognjen Milic

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/26586 ,  H01L21/28079 ,  H01L29/1045 ,  H01L29/41775 ,  H01L29/66492 ,  H01L29/66583

摘要： A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.

摘要翻译： 具有钨栅的全自对准晶体管。 单个掩模用于对准源极，漏极，栅极和隔离区域。 通过对这些区域使用单个掩码，覆盖误差大大降低。 中间间隙电极也与晶体管自对准。 电极优选由钨金属形成。

公开(公告)号：US08759912B2

公开(公告)日：2014-06-24

申请号：US13195199

申请日：2011-08-01

申请人： Donald R. Disney ,  Ognjen Milic ,  Kun Yi

发明人： Donald R. Disney ,  Ognjen Milic ,  Kun Yi

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66659

摘要： A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

摘要翻译： 高压晶体管器件包括在高压晶体管器件的漏极区域和源极区域之间的第一阱区域上的螺旋电阻场板，其中螺旋形电阻场板通过第一隔离与第一阱区域分离 并且耦合在漏极区域和源极区域之间。 高压晶体管器件还包括在螺旋电阻场板上的多个第一场板，每个第一场板覆盖螺旋电阻场板的一个或多个段，其中多个第一场板与螺旋电阻隔离 并且其中所述多个第一场板彼此隔离，并且起始第一场板连接到所述源极区域。

公开(公告)号：US20130043532A1

公开(公告)日：2013-02-21

申请号：US13212097

申请日：2011-08-17

申请人： Donald R. Disney ,  Ognjen Milic

发明人： Donald R. Disney ,  Ognjen Milic

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.

摘要翻译： 本公开公开了一种横向高压晶体管及其制造方法。 横向高压晶体管包括第一导电类型的半导体层; 在半导体层中与第一导电类型相反的第二导电类型的源极区; 所述半导体层中的所述第二导电类型的漏极区域与所述源极区域分离; 在源极区域和漏极区域之间的半导体层顶部的第一隔离层; 围绕所述漏极区的所述第二导电类型的第一阱区，朝向所述源极区延伸并与所述源极区分离; 围绕源区的第一导电类型的第二阱区; 位于所述第二阱区域上方的所述第一隔离层顶部的栅极和所述第一阱区域的相邻部分; 以及与所述横向高压晶体管的源极侧相邻的所述第一阱区域之下的所述第一导电类型的第一掩埋层。 使用栅极作为JFET顶栅形成JFET，并且将第一掩埋层形成为JFET底栅。

公开(公告)号：US20120104467A1

公开(公告)日：2012-05-03

申请号：US12916270

申请日：2010-10-29

申请人： Tiesheng Li ,  Ognjen Milic ,  Lei Zhang

发明人： Tiesheng Li ,  Ognjen Milic ,  Lei Zhang

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/8083 ,  H01L29/1066 ,  H01L29/66909

摘要： According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region. In another embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region.

摘要翻译： 根据一个实施例，自对准沟槽结构结栅场效应晶体管（JFET）包括硅衬底，在沟槽的底部附近具有P型多晶硅栅极区的两个或更多个沟槽和层间电介质层（ ILDL），分隔包括外延硅的每个沟槽的沟道区域，在每个沟槽的顶部之间延伸的沟道区域上方的N +源极区域和N +源极区域上方的源极金属之间的沟道区域。 在另一个实施例中，自对准沟槽结构JFET包括硅衬底，在沟槽的底部附近具有N型多晶硅栅极区域的两个或更多个沟槽和N型多晶硅栅极区域上方的ILDL，沟道区域 分离包括外延硅的每个沟槽，在每个沟槽的顶部之间延伸的沟道区上方的P +源极区域和P +源极区域之上的源极金属。