Method and apparatus for performing health tests of units of a data
processing system
    3.
    发明授权
    Method and apparatus for performing health tests of units of a data processing system 失效
    用于对数据处理系统的单元执行健康测试的方法和装置

    公开(公告)号:US5210757A

    公开(公告)日:1993-05-11

    申请号:US593408

    申请日:1990-10-05

    摘要: A means for ascertaining the health, or basic operational status, of a system unit. A "health check" provides an indication of either "yes", the system unit is operational, or "no", the system unit is either inoperative or there is a question as to whether the system is operational. The test is performed by requesting that the system unit perform a high priority "short" operation and noting the response provided to the request; the actual execution of the request is unimportant and it is the response of the unit under test to the receipt of the request for a bus operation that is the actual indicator of the status of the unit being tested. The requested operation is not directed at the unit whose operational status is to be determined, but instead at a bus interface unit which performs bus operations for the unit to be tested and whose responses to requests for bus operations are effected by the operational status of the unit that is to be tested. The operation is not directed at an actual element in the bus interface unit, but at a phantom, or nonexistent, element.

    摘要翻译: 一种用于确定系统单元的健康或基本操作状态的方法。 “健康检查”提供“是”,系统单元运行或“否”的指示,系统单元不工作或者是否存在系统是否可操作的问题。 通过请求系统单元执行高优先级“短”操作并注意提供给请求的响应来执行测试; 请求的实际执行不重要,并且是接收到总线操作请求的被测单元的响应,该总线操作是正在测试的单元的状态的实际指示符。 所请求的操作不是针对要确定其操作状态的单元,而是指向执行待测单元的总线操作的总线接口单元,并且其对总线操作请求的响应由 要测试的单位 该操作不是针对总线接口单元中的实际元件,而是以幻像或不存在的元素。

    Apparatus and method of loading a control store memory of a central
subsystem
    5.
    发明授权
    Apparatus and method of loading a control store memory of a central subsystem 失效
    装载和加载中央子系统的控制存储器的方法

    公开(公告)号:US4914576A

    公开(公告)日:1990-04-03

    申请号:US943980

    申请日:1986-12-18

    IPC分类号: G06F9/24

    CPC分类号: G06F9/24

    摘要: A multiprocessor data processing system includes a system management facility which controls the loading of each control store in the respective multiprocessor. The system management facility generates a sequence of commands which puts a processor in load mode, initializes a control store address register, transfers firmware words from a main memory to the control store, resets the load mode, starts a verify operation and checks the result of the verify operation.

    摘要翻译: 多处理器数据处理系统包括系统管理设备,其控制相应多处理器中每个控制存储器的加载。 系统管理设备产生一系列使处理器处于加载模式的命令,初始化控制存储地址寄存器,将固件字从主存储器传输到控制存储器,复位加载模式,启动验证操作并检查结果 验证操作。

    Method for performing quality logic tests on data processing systems by
sequentially loading test microinstruction programs and operating
microinstruction programs into a single control store
    6.
    发明授权
    Method for performing quality logic tests on data processing systems by sequentially loading test microinstruction programs and operating microinstruction programs into a single control store 失效
    通过依次加载测试微指令程序并将微指令程序运行到单个控制存储器中,对数据处理系统执行质量逻辑测试的方法

    公开(公告)号:US5173903A

    公开(公告)日:1992-12-22

    申请号:US583741

    申请日:1990-09-14

    IPC分类号: G06F11/22

    CPC分类号: G06F11/22

    摘要: A method for performing initial testing of a system wherein, in response to power on of the system, the control store of a central subsystem is loaded with a testing microinstruction program for internal testing of the central subsystem and the testing program executed. Upon completion of the testing program, the central subsystem operating programs are loaded into the control store, and control of the data processing system is transferred to the system programs.

    摘要翻译: 一种用于执行系统的初始测试的方法,其中响应于系统的通电,中央子系统的控制存储装载有用于中央子系统和所执行的测试程序的内部测试的测试微指令程序。 完成测试程序后,将中央子系统操作程序加载到控制存储区,并将数据处理系统的控制传送到系统程序。

    Method and apparatus for adapting a remote communications controller to
a variety of types of communications modems
    7.
    发明授权
    Method and apparatus for adapting a remote communications controller to a variety of types of communications modems 失效
    用于将远程通信控制器适配到各种类型的通信调制解调器的方法和装置

    公开(公告)号:US5202963A

    公开(公告)日:1993-04-13

    申请号:US629745

    申请日:1990-12-18

    申请人: Richard C. Zelley

    发明人: Richard C. Zelley

    IPC分类号: G06F13/10 H04L12/28 H04M11/06

    摘要: A data processing system includes at least one modem connected from a communications link to the remote devices and at least one modem controller. A modem adaptor stores scripts for directing modem control related operation, each script being a sequence of links and each link directing a modem control related operation, a library of modem control subroutines, each subroutine corresponding to a link, and a link table relating each link to the corresponding subroutine. There is a set of scripts for each type of modem connected to the system.

    摘要翻译: 数据处理系统包括从至少一个调制解调器控制器的通信链路连接到至少一个调制解调器。 调制解调器适配器存储用于指示调制解调器控制相关操作的脚本,每个脚本是一系列链接,每个链接指示调制解调器控制相关操作,调制解调器控制子程序库,对应于链接的每个子例程以及与每个链接相关联的链接表 到相应的子程序。 连接到系统的每种类型的调制解调器都有一组脚本。

    Memory architecture for facilitating optimum replaceable unit (ORU)
detection and diagnosis
    8.
    发明授权
    Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis 失效
    用于促进最佳可替换单元(ORU)检测和诊断的存储器架构

    公开(公告)号:US4563736A

    公开(公告)日:1986-01-07

    申请号:US509265

    申请日:1983-06-29

    CPC分类号: G06F11/267 G06F11/20

    摘要: A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and control circuits of the memory ports and CPU are included within the computer main board while memory modules/pacs are contained on one or more memory daughter boards which plug into memory input/output connectors contained on the main board. The port address and data paths connect in common to the memory connectors for transmitting and receiving memory addresses and data between the memory modules and the CPU and I/O ports. At least one register connects between the CPU and to common address path. When the CPU is placed in a diagnostic mode of operation, this register together with existing data registers are conditioned to store signals representative of the address and data being transmitted to the memory modules enabling the CPU to diagnose whether the main board or portions thereof has failed without requiring any testing of the memory modules.

    摘要翻译: 单个计算机板数据处理系统包括可通过I / O控制器通过系统总线I / O存储器端口或通过CPU存储器端口直接由系统的中央处理器(CPU)访问的多端口存储器系统。 存储器端口和CPU的逻辑和控制电路被包括在计算机主板内,而存储器模块/ pac被包含在插入到主板上的存储器输入/输出连接器的一个或多个存储器子板上。 端口地址和数据路径共同连接到存储器连接器,用于在存储器模块与CPU和I / O端口之间发送和接收存储器地址和数据。 至少有一个寄存器连接在CPU和公共地址路径之间。 当CPU处于诊断操作模式时,该寄存器与现有数据寄存器一起被调节为将表示正在发送的地址和数据的信号存储到存储器模块,使得CPU能够诊断主板或其部分是否已经失败 而不需要对内存模块进行任何测试。