公开(公告)号：US5379378A

公开(公告)日：1995-01-03

申请号：US773752

申请日：1991-10-10

申请人： Arthur Peters ,  Richard C. Zelley ,  Elmer W. Carroll ,  George J. Barlow ,  Chester M. Nibby, Jr. ,  James W. Keeley

发明人： Arthur Peters ,  Richard C. Zelley ,  Elmer W. Carroll ,  George J. Barlow ,  Chester M. Nibby, Jr. ,  James W. Keeley

IPC分类号： G06F13/362 ,  G06F13/26 ,  G06F13/38 ,  G06F13/42 ,  G06F15/16

CPC分类号： G06F13/4243

摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.

摘要翻译： 数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。 任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。 如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

公开(公告)号：US5274797A

公开(公告)日：1993-12-28

申请号：US377785

申请日：1989-07-06

申请人： George J. Barlow ,  Elmer W. Carroll ,  James W. Keeley ,  Wallace A. Martland ,  Victor M. Morganti ,  Arthur Peters ,  Richard C. Zelley

发明人： George J. Barlow ,  Elmer W. Carroll ,  James W. Keeley ,  Wallace A. Martland ,  Victor M. Morganti ,  Arthur Peters ,  Richard C. Zelley

IPC分类号： G01P1/00 ,  G01P15/08 ,  G01P15/097 ,  G01P15/10 ,  G06F11/00 ,  G06F11/22 ,  G06F11/273 ,  G06F11/30 ,  G06F11/32 ,  G06F11/36 ,  G06F15/16

CPC分类号： G01P15/097 ,  G01P1/003 ,  G01P15/0802 ,  G06F11/22 ,  G06F11/328 ,  G01P2015/0828 ,  G06F11/0757 ,  G06F11/2294 ,  G06F11/32 ,  G06F11/321

摘要： A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources which provide apparatus for indicating the status of power and temperature, booting the subsystems, testing the subsystems, timing central subsystem functions, and allowing local and remote maintenance access to the subsystems. The system management facility receives commands from the central subystem to read from and write into the timers as well as to read the status of the overall system. The system management facility generates special commands to the central subsystem to indicate when the timers have decremented to ZERO as well as special commands to aid in hardware and software debugging.

摘要翻译： 数据处理单元包括多个紧密耦合的中央子系统，多个外围子系统，主存储器和系统管理设备，其全部共同连接到系统总线。 系统管理单元在系统总线上具有最高优先级，并且包括提供用于指示功率和温度状态的设备，引导子系统，测试子系统，定时中心子系统功能以及允许本地和远程维护对子系统的访问的集中资源 。 系统管理设施接收来自中央子系统的命令，以读取和写入定时器以及读取整个系统的状态。 系统管理设备向中央子系统生成特殊命令，以指示定时器什么时候减少到零，以及特殊命令来辅助硬件和软件调试。

公开(公告)号：US4910666A

公开(公告)日：1990-03-20

申请号：US943984

申请日：1986-12-18

申请人： Chester M. Nibby, Jr. ,  Richard C. Zelley ,  Kenneth E. Bruce ,  George J. Barlow ,  James W. Keeley

发明人： Chester M. Nibby, Jr. ,  Richard C. Zelley ,  Kenneth E. Bruce ,  George J. Barlow ,  James W. Keeley

IPC分类号： G06F9/445 ,  G06F9/22 ,  G06F9/24

CPC分类号： G06F9/24

摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

公开(公告)号：US4833601A

公开(公告)日：1989-05-23

申请号：US55577

申请日：1987-05-28

申请人： George J. Barlow ,  James W. Keeley ,  Chester M. Nibby, Jr.

发明人： George J. Barlow ,  James W. Keeley ,  Chester M. Nibby, Jr.

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/16 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F11/073 ,  G06F11/0724 ,  G06F11/0793 ,  G06F12/0815 ,  G06F11/0757 ,  G06F11/141

摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

公开(公告)号：US4799222A

公开(公告)日：1989-01-17

申请号：US001124

申请日：1987-01-07

申请人： George J. Barlow ,  James W. Keeley ,  Chester M. Nibby, Jr.

发明人： George J. Barlow ,  James W. Keeley ,  Chester M. Nibby, Jr.

IPC分类号： G06F11/10 ,  G06F12/08 ,  G06F12/10 ,  G06F12/16

CPC分类号： G06F11/10 ,  G06F12/0802

摘要： An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.

摘要翻译： 从多个源传送地址的地址路径包括递增电路。 地址包括多个地址位和完整性位。 地址位应用于递增电路，而完整性位并行应用于可编程逻辑器件（PLD）。 当地址正在根据需要被传送或递增时，PLD独立地产生多个变换位，定义预测为改变状态的地址位数的特性。 此后，变换位用于变换用于递增地址的传送的地址完整性位。 逻辑地组合递增地址，变换位和完整性位，以验证地址是否被传送和/或递增而没有错误。

公开(公告)号：US5210757A

公开(公告)日：1993-05-11

申请号：US593408

申请日：1990-10-05

申请人： George J. Barlow ,  Richard C. Zelley ,  James W. Keeley

发明人： George J. Barlow ,  Richard C. Zelley ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F11/22 ,  G06F11/273

CPC分类号： G06F11/22 ,  G06F11/2736 ,  G06F11/0757

摘要： A means for ascertaining the health, or basic operational status, of a system unit. A "health check" provides an indication of either "yes", the system unit is operational, or "no", the system unit is either inoperative or there is a question as to whether the system is operational. The test is performed by requesting that the system unit perform a high priority "short" operation and noting the response provided to the request; the actual execution of the request is unimportant and it is the response of the unit under test to the receipt of the request for a bus operation that is the actual indicator of the status of the unit being tested. The requested operation is not directed at the unit whose operational status is to be determined, but instead at a bus interface unit which performs bus operations for the unit to be tested and whose responses to requests for bus operations are effected by the operational status of the unit that is to be tested. The operation is not directed at an actual element in the bus interface unit, but at a phantom, or nonexistent, element.

摘要翻译： 一种用于确定系统单元的健康或基本操作状态的方法。 “健康检查”提供“是”，系统单元运行或“否”的指示，系统单元不工作或者是否存在系统是否可操作的问题。 通过请求系统单元执行高优先级“短”操作并注意提供给请求的响应来执行测试; 请求的实际执行不重要，并且是接收到总线操作请求的被测单元的响应，该总线操作是正在测试的单元的状态的实际指示符。 所请求的操作不是针对要确定其操作状态的单元，而是指向执行待测单元的总线操作的总线接口单元，并且其对总线操作请求的响应由 要测试的单位 该操作不是针对总线接口单元中的实际元件，而是以幻像或不存在的元素。

公开(公告)号：US4724519A

公开(公告)日：1988-02-09

申请号：US750117

申请日：1985-06-28

申请人： George J. Barlow ,  James W. Keeley ,  Elmer W. Carroll

发明人： George J. Barlow ,  James W. Keeley ,  Elmer W. Carroll

IPC分类号： G06F13/14 ,  G06F12/06 ,  G06F13/362 ,  G06F13/368 ,  G06F13/378 ,  G06F13/36

CPC分类号： G06F13/368 ,  G06F12/0623 ,  G06F13/378

摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.

摘要翻译： 数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。 每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。 子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。 每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。 在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值 。

公开(公告)号：US5491790A

公开(公告)日：1996-02-13

申请号：US231856

申请日：1994-04-22

申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Keith L. Petry ,  Thomas S. Hirsch

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F9/445 ,  G06F11/22 ,  G06F11/267

CPC分类号： G06F11/2236 ,  G06F11/22 ,  G06F9/4403

摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

摘要翻译： 除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。 在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

公开(公告)号：US5341501A

公开(公告)日：1994-08-23

申请号：US771582

申请日：1991-10-04

申请人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

发明人： James W. Keeley ,  Richard A. Lemay ,  Chester M. Nibby, Jr.

IPC分类号： G06F13/368 ,  G06F9/46

CPC分类号： G06F13/368

摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

摘要翻译： 高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。 电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。 所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟 当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

公开(公告)号：US4764862A

公开(公告)日：1988-08-16

申请号：US717201

申请日：1985-03-28

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F13/42 ,  G06F13/14

CPC分类号： G06F13/4213 ,  G06F11/00

摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

摘要翻译： 数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。 每个单元包括用于确认从其他单元接收的请求的响应装置。 多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。 当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。 这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。