Method and apparatus for memory retry
    1.
    发明授权
    Method and apparatus for memory retry 失效
    用于记忆重试的方法和装置

    公开(公告)号:US5210867A

    公开(公告)日:1993-05-11

    申请号:US593182

    申请日:1990-10-05

    IPC分类号: G06F11/14

    CPC分类号: G06F11/1402

    摘要: Memory retry logic to improve the resilience of system memory operations with respect to system errors or faults which prevent a memory read operation from being completed on a first attempt by allowing the memory to retry the operation once. The memory retry logic detects the occurrence of an improper response from the system element requesting a memory read operation when attempting to initiate the system bus operation for reading the data from memory to the requesting element and, if an improper response indicating that the requesting element is not accepting the bus operation request is detected, stores the memory operation request and the requested data and retries the data transmission on the next available bus cycle. If the memory receives an improper response of a specified type during a bus operation of a memory burst, the memory will terminate the operation and proceed to the next requested operation.

    摘要翻译: 存储器重试逻辑以提高系统存储器操作相对于系统错误或故障的弹性,从而通过允许存储器重试操作一次来防止存储器读取操作在第一次尝试中完成。 当尝试启动用于从存储器读取数据到请求单元的系统总线操作时,存储器重试逻辑检测到来自系统元件的不正确响应的发生,请求存储器读取操作,并且如果指示请求元素是不正确的响应 不接受检测到总线操作请求,存储存储器操作请求和请求的数据,并在下一个可用的总线周期重试数据传输。 如果在存储器突发的总线操作期间存储器接收到指定类型的不正确响应,则存储器将终止操作并进行下一个所请求的操作。

    Method and apparatus for resetting a memory upon power recovery
    2.
    发明授权
    Method and apparatus for resetting a memory upon power recovery 失效
    电源恢复时重置存储器的方法和装置

    公开(公告)号:US5204964A

    公开(公告)日:1993-04-20

    申请号:US593917

    申请日:1990-10-05

    摘要: A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.

    摘要翻译: 一种当向系统施加电力时复位存储器状态的方法和装置。 存储器具有存储器元件,刷新时钟和刷新计数器,用于对刷新周期进行计数,并向存储器元件提供刷新信号,存储器元件和刷新装置从电力系统和电池备用装置连接。 状态检测装置从刷新计数器连接,用于检测刷新计数器的状态改变到与刷新计数器的复位状态相当的状态,并且断言状态改变信号。 响应于状态改变信号和复位信号的发生的装置提供存储器控制器复位信号,使得存储器控制器复位信号与刷新计数器的状态改变同步到与刷新计数器相当的状态 复位状态。 存储器复位还包括响应于重置信号的断言和与刷新计数器同步来刷新周期的刷新时钟的超时计数器装置。 超时检测装置响应于超时计数器装置,用于当超时计数器已经计数了刷新周期加一个时钟周期时提供超时信号,以及当状态改变信号提供存储器控制器复位信号时 超时计数器已经计数了刷新周期加上一个时钟周期,状态改变信号还没有被断言。