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13 条记录 (耗时 0.05 秒)

    Method and apparatus for resetting a memory upon power recovery
    1.
    发明授权
    Method and apparatus for resetting a memory upon power recovery 失效
    电源恢复时重置存储器的方法和装置

    公开(公告)号：US5204964A

    公开(公告)日：1993-04-20

    申请号：US593917

    申请日：1990-10-05

    申请人： Raymond D. Bowden, III ,  Michelle A. Pence ,  George J. Barlow ,  Marc E. Sanfacon ,  Jeffrey S. Somers

    发明人： Raymond D. Bowden, III ,  Michelle A. Pence ,  George J. Barlow ,  Marc E. Sanfacon ,  Jeffrey S. Somers

    IPC分类号： G06F11/14 ,  G06F11/20 ,  G11C7/20 ,  G11C11/406

    CPC分类号： G06F11/1441 ,  G11C11/406 ,  G11C7/20 ,  G06F11/2015

    摘要： A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.

    摘要翻译： 一种当向系统施加电力时复位存储器状态的方法和装置。 存储器具有存储器元件，刷新时钟和刷新计数器，用于对刷新周期进行计数，并向存储器元件提供刷新信号，存储器元件和刷新装置从电力系统和电池备用装置连接。 状态检测装置从刷新计数器连接，用于检测刷新计数器的状态改变到与刷新计数器的复位状态相当的状态，并且断言状态改变信号。 响应于状态改变信号和复位信号的发生的装置提供存储器控制器复位信号，使得存储器控制器复位信号与刷新计数器的状态改变同步到与刷新计数器相当的状态 复位状态。 存储器复位还包括响应于重置信号的断言和与刷新计数器同步来刷新周期的刷新时钟的超时计数器装置。 超时检测装置响应于超时计数器装置，用于当超时计数器已经计数了刷新周期加一个时钟周期时提供超时信号，以及当状态改变信号提供存储器控制器复位信号时 超时计数器已经计数了刷新周期加上一个时钟周期，状态改变信号还没有被断言。

    Memory controller with error logging
    3.
    发明授权
    Memory controller with error logging 失效
    具有错误记录的内存控制器

    公开(公告)号：US4964129A

    公开(公告)日：1990-10-16

    申请号：US287927

    申请日：1988-12-21

    申请人： Raymond D. Bowden, III ,  Edward R. Salas ,  Marc E. Sanfacon ,  Jeffrey S. Somers

    发明人： Raymond D. Bowden, III ,  Edward R. Salas ,  Marc E. Sanfacon ,  Jeffrey S. Somers

    IPC分类号： G06F11/07 ,  G06F11/10

    CPC分类号： G06F11/106 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/079

    摘要： In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

    摘要翻译： 根据本发明，提供了一种用于记录在数据处理系统中的多芯片存储器存储装置中发生的错误的系统。 该系统具有用于检测错误并用于接收与其相关联的数据和校验位的机制。 用于检测错误的机制产生作为数据和校验位的函数的校正子位。 连接到错误检测机制的是错误记录机制，其适于接收校正子位并确定发生错误的芯片。

    High performance burst read data transfer operation
    4.
    发明授权
    High performance burst read data transfer operation 失效
    高性能突发读取数据传输操作

    公开(公告)号：US5291580A

    公开(公告)日：1994-03-01

    申请号：US771703

    申请日：1991-10-04

    申请人： Raymond D. Bowden, III ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Jeffrey S. Somers

    发明人： Raymond D. Bowden, III ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Jeffrey S. Somers

    IPC分类号： G06F13/42 ,  G06F13/28

    CPC分类号： G06F13/4243

    摘要： A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

    摘要翻译： 存储器系统通过同步总线紧密耦合到高性能微处理器。 包括在存储器系统中的逻辑电路使用不同于用于同步微处理器和存储器操作的边缘的时钟脉冲信号的连续转换来产生blipper脉冲信号。 blipper脉冲信号与存储器的列地址选通定时信号进行逻辑结合，该定时信号是从时钟脉冲信号的同步边沿导出的，该时钟脉冲信号定义在连续存储器周期期间访问一对DRAM存储器所需的列地址间隔的持续时间，以提供 四个内存读取响应的序列，无等待状态。