公开(公告)号：US20080037428A1

公开(公告)日：2008-02-14

申请号：US11873585

申请日：2007-10-17

申请人： George Nation ,  Gurumani Senthil ,  Gary Delp

发明人： George Nation ,  Gurumani Senthil ,  Gary Delp

IPC分类号： G08C15/00

CPC分类号： H04L47/39 ,  H04L47/10 ,  H04L47/30 ,  H04L49/90

摘要： Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.

摘要翻译： 用于标准化，高速串行通信的方法和结构，以减少高速串行通信信道的接收元件内的存储容量要求。 在本发明的示例性SPI兼容实施例中，修改STARVING，HUNGRY和SATISFIED流控制状态的语义意义，以允许发送和接收元件以更有效的方式来管理缓冲存储器，从而降低存储容量要求，同时保持 流动控制合同和承诺的完整性。 所述方法和结构进一步提供用于产生存储度量信息以便相对于数据分组传输异步地动态地更新流控制状态信息。

公开(公告)号：US20060236292A1

公开(公告)日：2006-10-19

申请号：US11079439

申请日：2005-03-14

申请人： Gary Delp ,  George Nation

发明人： Gary Delp ,  George Nation

IPC分类号： G06F17/50 ,  H03K17/693

CPC分类号： G06F17/505 ,  G06F17/5054

摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

公开(公告)号：US08239700B2

公开(公告)日：2012-08-07

申请号：US12425532

申请日：2009-04-17

申请人： George Nation ,  Jon W. Byrn ,  Gary Delp

发明人： George Nation ,  Jon W. Byrn ,  Gary Delp

IPC分类号： G06F1/32

CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/16

摘要： Various embodiments of the present invention provide systems and methods for governing power dissipation in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include a first function circuit, a second function circuit, and a power state change control circuit. The power state change control circuit is operable to determine a combination of power states of the first function circuit and the second function circuit that provides an overall power dissipation within a power dissipation level.

摘要翻译： 本发明的各种实施例提供了一种用于控制半导体器件中功率耗散的系统和方法。 例如，本发明的各种实施例提供了包括第一功能电路，第二功能电路和电源状态改变控制电路的半导体器件。 电源状态改变控制电路可操作以确定提供功耗级别内的总功率消耗的第一功能电路和第二功能电路的功率状态的组合。

公开(公告)号：US20100269074A1

公开(公告)日：2010-10-21

申请号：US12425547

申请日：2009-04-17

申请人： George Nation ,  Jon W. Byrn ,  Gary Delp

发明人： George Nation ,  Jon W. Byrn ,  Gary Delp

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Various embodiments of the present invention provide systems and methods for improved semiconductor design. For example, various embodiments of the present invention provide methods for semiconductor design that include receiving a semiconductor design with at least a first function circuit and a second function circuit; simulating the semiconductor design using a first instruction and a second instruction; determining a power state transition between the first instruction and the second instruction; and augmenting the semiconductor design to implement the determined power state transition. Simulating the semiconductor design using a first instruction and a second instruction identifies an indication of a first subset of the first function circuit and the second function circuit used in executing the first instruction and a second subset of the first function circuit and the second function circuit used in executing the second instruction. The power state transition accommodates at least one power attribute selected from a group consisting of: an inrush current value, and an overall power dissipation value.

摘要翻译： 本发明的各种实施例提供了用于改进半导体设计的系统和方法。 例如，本发明的各种实施例提供了用于半导体设计的方法，包括至少接收具有第一功能电路和第二功能电路的半导体设计; 使用第一指令和第二指令来模拟半导体设计; 确定所述第一指令和所述第二指令之间的功率状态转换; 并且增加半导体设计以实现所确定的功率状态转换。 使用第一指令和第二指令来模拟半导体设计，识别用于执行第一指令的第一功能电路和第二功能电路的第一子集的指示，以及使用的第一功能电路和第二功能电路的第二子集 在执行第二条指令时。 功率状态转换适应从由以下组成的组中选择的至少一个功率属性：浪涌电流值和总功耗值。

公开(公告)号：US20100268917A1

公开(公告)日：2010-10-21

申请号：US12425507

申请日：2009-04-17

申请人： George Nation ,  Jon W. Byrn ,  Gary Delp

发明人： George Nation ,  Jon W. Byrn ,  Gary Delp

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/171

摘要： Various embodiments of the present invention provide systems and methods for ramping current usage in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include at least a first function circuit and a second function circuit, and a power state change control circuit. The power state change control circuit is operable to transition the power state of the first function circuit from a reduced power state to an operative power state, and to transition the second function circuit from a reduced power state to an operative power state. Transition of the power state of at least one of the first function circuit and the second function circuit is done in at least a first stage at a first time and a second stage at a second time, with the second time being after the first time.

摘要翻译： 本发明的各种实施例提供了用于在半导体器件中斜升电流使用的系统和方法。 例如，本发明的各种实施例提供了至少包括第一功能电路和第二功能电路以及电源状态改变控制电路的半导体器件。 电源状态改变控制电路可操作以将第一功能电路的电源状态从降低功率状态转换到工作电源状态，并将第二功能电路从降低功率状态转换到工作电源状态。 第一功能电路和第二功能电路中的至少一个功率状态的转换在第一时间和第二阶段的至少第一阶段中进行，第二次是第一次。

公开(公告)号：US20100264983A1

公开(公告)日：2010-10-21

申请号：US12425532

申请日：2009-04-17

申请人： George Nation ,  Jon W. Byrn ,  Gary Delp

发明人： George Nation ,  Jon W. Byrn ,  Gary Delp

IPC分类号： G05F1/10

CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/16

摘要： Various embodiments of the present invention provide systems and methods for governing power dissipation in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include a first function circuit, a second function circuit, and a power state change control circuit. The power state change control circuit is operable to determine a combination of power states of the first function circuit and the second function circuit that provides an overall power dissipation within a power dissipation level.

摘要翻译： 本发明的各种实施例提供了一种用于控制半导体器件中功率耗散的系统和方法。 例如，本发明的各种实施例提供了包括第一功能电路，第二功能电路和电源状态改变控制电路的半导体器件。 电源状态改变控制电路可操作以确定提供功耗级别内的总功率消耗的第一功能电路和第二功能电路的功率状态的组合。

公开(公告)号：US20070124716A1

公开(公告)日：2007-05-31

申请号：US11290186

申请日：2005-11-30

申请人： George Nation ,  Gary Lippert ,  Gary Delp

发明人： George Nation ,  Gary Lippert ,  Gary Delp

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.

摘要翻译： 一种用于在设计捕获环境中概括设计属性的方法，包括以下步骤：（A）定义用于将一个或多个辅助配置器添加到工具或工具套件的过程，（B）将辅助配置器链接到抽象的预定对象点 设计和（C）定义用于参考一个或多个辅助配置器的工具或工具套件的过程，其中辅助配置器既不被核心引用也不内置在工具或工具套件中。

公开(公告)号：US20060236270A1

公开(公告)日：2006-10-19

申请号：US11079028

申请日：2005-03-14

申请人： Gary Delp ,  George Nation

发明人： Gary Delp ,  George Nation

IPC分类号： G06F17/50 ,  H03K19/173 ,  H01L21/00 ,  H01L23/02 ,  G06F7/38

CPC分类号： G06F17/5045 ,  G06F2217/64

摘要： An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.

公开(公告)号：US20050240892A1

公开(公告)日：2005-10-27

申请号：US11156319

申请日：2005-06-18

申请人： Robert Broberg ,  Jonathan Byrn ,  Gary Delp ,  Michael Eneboe ,  Gary McClannahan ,  George Nation ,  Paul Reuland ,  Thomas Sandoval ,  Matthew Wingren

发明人： Robert Broberg ,  Jonathan Byrn ,  Gary Delp ,  Michael Eneboe ,  Gary McClannahan ,  George Nation ,  Paul Reuland ,  Thomas Sandoval ,  Matthew Wingren

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US20070096303A1

公开(公告)日：2007-05-03

申请号：US11260334

申请日：2005-10-27

申请人： Gary Delp

发明人： Gary Delp

IPC分类号： H01L23/34 ,  H01L21/00

CPC分类号： H01L23/5386 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/24226 ,  H01L2224/81801 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2224/86 ,  H01L2924/14 ,  H01L2924/00

摘要： An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

摘要翻译： 一种装置包括第一半导体管芯和至少一个另外的半导体管芯。 衬底附接到第一裸片和另一裸片，并且具有将第一裸片上的触点与另一裸片上的相应触点互连的电互连图案。 互连图案的特征在基板上具有相对于第一裸片上的触点的位置具有比在另一裸片上的触点的位置更小的公差的位置。