-
1.发明授权Efficient point-to-point and multi-point routing mechanism for programmable packet switching nodes in high speed data transmission networks 失效高速数据传输网络中可编程分组交换节点的高效点对点和多点路由机制
公开(公告)号：US5602841A
公开(公告)日：1997-02-11
申请号：US404800
申请日：1995-03-15
申请人： Gerald Lebizay , Jean M. Munier , Andre Pauporte , Victor Spagnol
发明人： Gerald Lebizay , Jean M. Munier , Andre Pauporte , Victor Spagnol
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/201 , H04L49/3081 , H04L2012/5642 , H04L49/25
摘要： The present invention relates to an efficient point-to-point and multi-points routing system and method for programmable data communication adapters in packet switching nodes of high speed networks. The general principles of this efficiency are the following:First, data packets are never copied, only packet pointers are copied for each destination: Space in Buffer Memory is saved, the number of instructions is significantly reduced improving the packet throughput (number of packets per seconds that the adapter is able to transmit). and the routing is independant of the packets length.Second, no overhead is generated by the multi-points mechanism in the real time procedures: the underrun/overrun problems on the ouputs are reduced and the efficiency of the adapter in term data throughput (bits per second) is significantly improved.Third, each output is processed independently by means of interrupts: lines are managed in real time and lines of different speed or protocol can be supported in parallel.Fourth, the release of the resources is entirely realized on a non priority mode.
摘要翻译： 本发明涉及一种用于高速网络的分组交换节点中的可编程数据通信适配器的有效的点对点和多点路由系统和方法。 这种效率的一般原则如下：首先，数据包不会被复制，每个目的地只复制数据包指针：缓冲存储器中的空间被保存，指令数量显着减少，从而提高了数据包吞吐量（每个数据包的数量 适配器能够传输的秒数）。 路由独立于报文长度。 其次，多点机制在实时程序中不产生任何开销：输出上的欠载/溢出问题减少，适配器在术语数据吞吐量（每秒位数）中的效率得到显着提高。 第三，每个输出通过中断独立处理：线路实时管理，并行支持不同速度或协议的线路。 第四，资源的释放在非优先模式下完全实现。
-
2.发明授权Programmable high performance data communication adapter for high speed packet transmission networks 失效可编程高性能数据通信适配器，用于高速分组传输网络
公开(公告)号：US5528587A
公开(公告)日：1996-06-18
申请号：US252299
申请日：1994-06-01
申请人： Claude Galand , Gerald Lebizay , Daniel Mauduit , Jean-marie Munier , Andre Pauporte , Eric Saint-Georges , Victor Spagnol
发明人： Claude Galand , Gerald Lebizay , Daniel Mauduit , Jean-marie Munier , Andre Pauporte , Eric Saint-Georges , Victor Spagnol
CPC分类号： H04L29/06
摘要： A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprisesmeans for buffering (132) said data packets,means for identifying said buffering means and said data packets in said buffering means,means for queueing (FIG. 15) in storing means (131) said identifying means in a single instruction,means for dequeueing (FIG. 16) from said storing (131) means said identifying means in another single instruction,means for releasing said buffering means,Each instruction comprises up to three operations executed in parallel by said processing means:an arithmetical and logical (ALU) operation on said identifying means,memory operation on said storing means, anda sequence operation.
摘要翻译： 公开了一种用于高速分组传输网络的高性能数据分组缓冲方法和可编程数据通信适配器。 线路适配器包括可编程处理装置，用于接收和发送具有固定或可变长度的数据分组。 该系统的特征在于它包括用于缓冲（132）所述数据分组的装置，用于识别所述缓冲装置中的所述缓冲装置和所述数据分组的装置，用于在存储装置（131）中排队（图15）的装置，所述识别装置 在单个指令中，用于从所述存储器（131）取出的装置（图16）意味着在另一单个指令中的所述识别装置，用于释放所述缓冲装置的装置。每个指令包括由所述处理装置并行执行的多达三个操作： 对所述识别装置进行算术和逻辑（ALU）操作，对所述存储装置进行存储操作和顺序操作。
-
3.发明授权Interface for independently establishing a link and transmitting high level commands including logical addresses from dedicated microprocessor to shared intelligent memory 失效接口独立建立链接并发送高级别命令，包括从专用微处理器到共享的智能存储器的逻辑地址
公开(公告)号：US5148527A
公开(公告)日：1992-09-15
申请号：US440569
申请日：1989-11-22
IPC分类号： G06F15/16 , G06F9/46 , G06F12/06 , G06F13/16 , G06F15/167 , G06F15/177
CPC分类号： G06F9/544 , G06F13/1652 , G06F13/1663 , G06F9/546
摘要： In a shared memory system, wherein several memory users MU wish access to a plurality of memory banks, a set of high level commands (CREATE, PUT, GET, RELEASE) is provided, to transfer data between a given memory user and the memory banks or another memory user. The high level commands sent by the memory users are built up by memory interfaces MI connected to the memory users, and transmitted through an interconnection network to Packet Memory Command Executors PMCE integrated into each memory bank. The high level commands work with data records identified by Logical Record Addresses (LRA) known by the memory users. During execution of the high level commands by the PMCE, the LRA are translated into physical addresses corresponding to physical address space in the memory banks. The physical address space is created dynamically and released upon need, through the Create or Release Commands.A given memory user is not involved at all by management of physical address space, and works only with the LRA of a record.
-
4.发明授权Method and system for implementing relative time discriminations in a high speed data transmission network 失效在高速数据传输网络中实现相对时间识别的方法和系统
公开(公告)号：US5721944A
公开(公告)日：1998-02-24
申请号：US498133
申请日：1995-07-05
CPC分类号： H04L12/5602 , H04L2012/5637
摘要： A data transmission network congestion control mechanism requires knowledge of the sequence of occurrence of two dates d1 and d2, respectively defined by times t1 and t2 provided by a wraparound timer as respective numbers A and B coded in a 2's-complement form. Relative date discrimination is implemented by dividing the wraparound timer period into four consecutive intervals, each defined by the two most significant bits of the timer count. The value of the most significant bits and the sign of A-B, are used to derive a one-bit "X" indicator, the binary value of which indicates which of the two dates d1 and d2 was first to occur.
摘要翻译： 数据传输网络拥塞控制机制需要知道由包绕定时器提供的时间t1和t2分别限定的两个日期d1和d2的发生顺序，作为以2'-互补形式编码的相应数字A和B。 相对日期识别通过将环绕定时器周期划分为四个连续的间隔来实现，每个间隔由定时器计数的两个最高有效位定义。 最高有效位的值和A-B的符号用于导出一位“X”指示符，其二进制值表示两个日期d1和d2中的哪一个首先发生。
-
5.发明授权Non-locking queueing mechanism for enabling a receiver device to read from a queue without access synchronization with a sending device 失效非锁定排队机制，用于使接收器设备能够从队列中读取而不与发送设备进行访问同步
公开(公告)号：US4980852A
公开(公告)日：1990-12-25
申请号：US139873
申请日：1987-12-29
CPC分类号： G06F5/12 , G06F5/065 , G06F2205/123
摘要： A non-locking queueing mechanism is described for transferring information from a sending unit to a receiving unit through a queue in which there is no interference between the independent units (sender and receiver) during enqueueing or dequeueing. The invention thus avoids any form of interlock or serialism. The mechanism includes a first pointer (D), identifying the element area in the queueing device where the last dequeued information element, if any, was located, and a second pointer register for logging a second pointer (E) identifying the element area in the queueing device where the last enqueued information element, if any, was located, a first control block activated by the sending unit to enqueue the information element into the queueing device and for updating the second pointer, and a second control block activated by the recieving unit to dequeue the information element from the queueing device and for updating the first pointer.
-
6.发明授权Device for loading and reading strings of latches in a data processing system 失效用于在数据处理系统中加载和读取锁存器串的装置
公开(公告)号：US4597042A
公开(公告)日：1986-06-24
申请号：US533188
申请日：1983-09-19
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318558
摘要： A device for loading data in and reading data out of latch strings located in field replaceable units containing the circuitry of a data processing system realized in accordance with the Level-Scan Sensitive Design (LSSD) technique. Each field replaceable unit includes an addressing circuit. The addressing circuits are interconnected by a monitoring loop over which a configuration of address bits is serially transmitted by a control circuit. The data to be loaded and read out propagate in a data loop and are entered in a latch string under control of the addressing circuit.
摘要翻译： 一种装置，用于将数据加载到位于包含根据级别扫描敏感设计（LSSD）技术实现的数据处理系统的电路的现场可更换单元中的锁存器串中的数据）。 每个现场可更换单元包括寻址电路。 寻址电路通过监视回路相互连接，通过该监视回路，地址位的配置由控制电路串行发送。 要加载和读出的数据在数据循环中传播，并在寻址电路的控制下输入到锁存字符串。
-
公开(公告)号：US06175910B1
公开(公告)日：2001-01-16
申请号：US09098297
申请日：1998-06-16
申请人： Andre Pauporte , Francois Jacob
发明人： Andre Pauporte , Francois Jacob
IPC分类号： G06F1500
CPC分类号： G06F9/30098 , G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/3885
摘要： The object of the present invention is to improve the execution of instructions using speculative operations in Superscalar or Very Long Instruction Word (VLIW) processors having multiple Arithmetic Logic Units (ALUs). More particularly, the invention relates to a system and method for using standard registers as shadow registers. The addresses of all standard registers are translated using a Relocation Table (RT) array. The addresses of registers used as shadow registers are translated another time using a Speculative Registers Table (SRT) array. At branch completion time, for the speculative operations that have previously been executed and correctly predicted, the Relocation Table (RT) is updated with the Speculative Registers Table (SRT) content. For the speculative operations that have previously been executed and incorrectly predicted, the Relocation Table (RT) remains unchanged. The present invention performs the same function as processors using state of the art hardware shadow registers while using a limited number of read/write ports standard register array.
摘要翻译： 本发明的目的是改进使用具有多个算术逻辑单元（ALU）的超标量或超长指令字（VLIW）处理器中的推测操作的指令的执行。 更具体地说，本发明涉及使用标准寄存器作为影子寄存器的系统和方法。 使用重定位表（RT）阵列翻译所有标准寄存器的地址。 用作影子寄存器的寄存器的地址使用推测寄存器表（SRT）阵列翻译另一次。 在分支完成时间，对于先前执行和正确预测的推测操作，重定位表（RT）将使用推测寄存器表（SRT）内容进行更新。 对于先前执行和错误预测的投机操作，重定位表（RT）保持不变。 本发明在使用有限数量的读/写端口标准寄存器阵列的同时，使用最先进的硬件影子寄存器执行与处理器相同的功能。
-
公开(公告)号：US5471581A
公开(公告)日：1995-11-28
申请号：US146770
申请日：1993-06-23
CPC分类号： G06F5/16 , G06F13/4059 , G06F2205/063
摘要： An elastic buffer is provided between two busses working with independent clocking. The buffer is implemented by a piece of RAM memory (37) partitioned into sectors (41), each of which contains successive memory addresses. Each sector (41), can be alternatively written and read, so that at a given moment, a sector in write mode and a sector in read mode may coexist. Each sector is controlled by a mark flag (MF), a set flag corresponding to a fully written sector, and a reset flag corresponding to a sector that has been read onto the destination bus. The mark flag of each sector is set, respectively reset, upon the event of a move in pointer, respectively move out pointer, reaching the next adjacent sector. For a given elastic buffer size, the size of the sectors (41) and the number of mark flags are adaptable to the specifications of the data flow between the origin and destination busses.
摘要翻译： 两台总线之间设有一个弹性缓冲器，可以独立运行。 缓冲器由划分成扇区（41）的一块RAM存储器（37）来实现，每个扇区（41）包含连续的存储器地址。 可以替代地写入和读取每个扇区（41），使得在给定时刻，写入模式中的扇区和读取模式中的扇区可以共存。 每个扇区由标记标志（MF），对应于完全写入的扇区的设置标志以及对应于已经读取到目的地总线上的扇区的复位标志来控制。 每个扇区的标记标志分别在指针移动的情况下分别复位，分别移出指针，到达下一个相邻扇区。 对于给定的弹性缓冲器大小，扇区（41）的大小和标记标志的数量适用于原始和目的地总线之间的数据流的规范。
-
公开(公告)号：US5235700A
公开(公告)日：1993-08-10
申请号：US641833
申请日：1991-01-16
申请人： Haissam Alaiwan , Jean Calvignac , Jacques-Louis Combes , Andre Pauporte , Claude Basso , Francois Kermarec
发明人： Haissam Alaiwan , Jean Calvignac , Jacques-Louis Combes , Andre Pauporte , Claude Basso , Francois Kermarec
CPC分类号： G06F11/2028 , G06F11/1658 , G06F11/2043
摘要： A device which switches data processing from an active processor, about to fail, to a back-up processor includes a memory change detector which captures memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establishing recovery point signals generated by the active processor to be dumped into the memory of the back-up processor so that the back-up processor resumes operation of the active processor from the last established recovery point.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.019 秒)
