公开(公告)号：US06236619B1

公开(公告)日：2001-05-22

申请号：US09559265

申请日：2000-04-27

Applicant: Geun-hee Cho ,  Chi-wook Kim

Inventor： Geun-hee Cho ,  Chi-wook Kim

IPC: G11C800

CPC classification number: G11C7/1072 ,  G11C7/22

Abstract: A synchronous dynamic random access memory (SDRAM) semiconductor device is provided. The SDRAM has a write-interrupt-write function and includes a first memory block for storing data, a first sense amplifier for sensing the data stored in the first memory block, first and second groups of input/output lines, connected to the first sense amplifier, and a write-interrupt-write signal generating portion for receiving an externally input write signal and an internal clock signal to generate a write-interrupt-write signal, and for providing the write-interrupt-write signal to the first sense amplifier. When an externally input data is written to the first memory block through the first group of input/output lines in response to the write signal enabled at a first point in time and the write signal is enabled at a second point in time to write data to the first memory block through the second group of input/output lines, the write-interrupt write signal generator enables the write-interrupt-write signal after a predetermined number of cycles of the internal clock signal from the second point in time at which the write signal is enabled, thereby immediately precharging the first group of input/output lines. As a result of this design, the write-interrupt-write function can be accurately carried out.

Abstract translation: 提供了一种同步动态随机存取存储器（SDRAM）半导体器件。 SDRAM具有写入中断写入功能，并且包括用于存储数据的第一存储器块，用于感测存储在第一存储器块中的数据的第一读出放大器，连接到第一感测的第一和第二组输入/输出线 放大器以及用于接收外部输入写入信号和内部时钟信号的写入中断写入信号产生部分，以产生写入中断写入信号，并向第一读出放大器提供写入中断写入信号。 当通过第一组输入/输出线将外部输入数据写入到第一存储块时，响应于在第一时间点使能写入信号，并且写入信号在第二时间点被使能以将数据写入 通过第二组输入/输出线的第一存储块，写中断写信号发生器在来自第二时间点的预定数量的内部时钟信号的周期之后启用写中断写信号， 信号被使能，从而立即对第一组输入/输出线进行预充电。 作为这种设计的结果，可以准确地执行写入中断写入功能。

公开(公告)号：US06898139B2

公开(公告)日：2005-05-24

申请号：US10773024

申请日：2004-02-05

Applicant: Jae-woong Lee ,  Chi-wook Kim ,  Sang-seok Kang

Inventor： Jae-woong Lee ,  Chi-wook Kim ,  Sang-seok Kang

IPC: G11C11/40 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C7/00

CPC classification number: G11C29/12015 ,  G11C7/1051 ,  G11C7/22 ,  G11C29/14

Abstract: Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Abstract translation: 集成电路存储器件包括被配置为以第一数据速率并行输出数据位的存储单元阵列。 输出电路被配置为在正常操作模式下以第一数据速率将数据位串行地输出到外部终端，并且以低于第一数据的第二数据速率将数据位串行输出到外部终端 在测试操作模式下的速率。 因此，在测试操作模式下，存储单元阵列可以以第一数据速率工作，同时允许输出电路以低于第一数据速率的第二数据速率将数据输出到外部终端。

公开(公告)号：US06526473B1

公开(公告)日：2003-02-25

申请号：US09440728

申请日：1999-11-16

Applicant: Chi-wook Kim

Inventor： Chi-wook Kim

IPC: G06F1202

CPC classification number: G11C7/1006 ,  G11C5/04

Abstract: A memory module system for connecting only selected memory modules to a data line to control data input and output is disclosed. The memory module system has a multiplicity of memory modules for outputting data to a data bus line, and more particularly, only the memory modules outputting data is electrically connected to the data bus line in response to activation of a predetermined connection control signal. The connection control signal has an activation width corresponding to a burst length of the output data. Only selected memory modules are connected to the data line during the data burst length, so that load per data pin is minimized, to thereby improve speed of writing and reading data.

Abstract translation: 公开了一种用于将所选存储器模块连接到数据线以控制数据输入和输出的存储器模块系统。 存储器模块系统具有用于将数据输出到数据总线的多个存储器模块，更具体地，响应于预定连接控制信号的激活，仅有输出数据的存储器模块电连接到数据总线。 连接控制信号具有对应于输出数据的突发长度的激活宽度。 在数据突发长度期间，只有选定的存储器模块连接到数据线，从而使每个数据引脚的负载最小化，从而提高写入和读取数据的速度。

公开(公告)号：US06324119B1

公开(公告)日：2001-11-27

申请号：US09557619

申请日：2000-04-25

Applicant: Chi-wook Kim

Inventor： Chi-wook Kim

IPC: G11C700

CPC classification number: G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/4093

Abstract: A data input circuit of a semiconductor memory device is disclosed. The data input circuit includes a control signal generation circuit, an internal strobe generation circuit and a data setup circuit. The control signal generation circuit generates a strobe control signal activated during input of data of the predetermined burst length. The internal strobe generation circuit generates an internal data strobe signal. The internal data strobe signal synchronizes with an external data strobe signal, and is disabled when data of the predetermined burst length is input. The data setup circuit converts sequentially input data to parallel data in response to the internal data strobe signal. According to the data input circuit and the data input method of the present invention, data of “high”-impedance cannot be input to the semiconductor memory device.

Abstract translation: 公开了一种半导体存储器件的数据输入电路。 数据输入电路包括控制信号发生电路，内部选通脉冲发生电路和数据建立电路。 控制信号产生电路产生在预定突发长度的数据输入期间激活的选通控制信号。 内部选通脉冲发生电路产生内部数据选通信号。 内部数据选通信号与外部数据选通信号同步，并且在输入预定突发长度的数据时被禁止。 数据设置电路响应于内部数据选通信号将顺序输入的数据转换成并行数据。 根据本发明的数据输入电路和数据输入方法，“高”阻抗的数据不能输入到半导体存储器件。

公开(公告)号：US6087851A

公开(公告)日：2000-07-11

申请号：US70894

申请日：1998-04-30

Applicant: Chi-wook Kim ,  Kyung-woo Kang

Inventor： Chi-wook Kim ,  Kyung-woo Kang

IPC: G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/0175

CPC classification number: H03K19/017581

Abstract: A semiconductor device can be configured for compatibility with different system level interfaces, e.g., LVTTL or SSTL, after assembly, thereby eliminating the need for bonding options and reducing the cost of manufacturing the device. The device includes an interface dependent circuit that operates with a selected interface in response to one or more interface enable signals. Several alternative embodiments include interface control circuits and mode register circuits for generating the interface enable signals responsive to a row address and control signals such as RAS, CAS, WE, and CS. Some embodiments also include a switching network that allows an input buffer to use an internally generated reference voltage for one interface and an externally applied reference voltage for a second interface.

Abstract translation: 半导体器件可以被配置为在组装之后与不同系统级接口（例如LVTTL或SSTL）兼容，从而消除对接合选项的需要并降低制造器件的成本。 该装置包括一个接口相关电路，该电路响应于一个或多个接口使能信号而与所选择的接口一起操作。 几个替代实施例包括接口控制电路和模式寄存器电路，用于响应于行地址和诸如RAS，CAS，WE和CS的控制信号来产生接口使能信号。 一些实施例还包括允许输入缓冲器对于一个接口使用内部产生的参考电压的开关网络和用于第二接口的外部施加的参考电压。

公开(公告)号：US20080031062A1

公开(公告)日：2008-02-07

申请号：US11775513

申请日：2007-07-10

Applicant: Soon-hong Ahn ,  Chi-wook Kim

Inventor： Soon-hong Ahn ,  Chi-wook Kim

IPC: G11C7/00 ,  G11C7/02

CPC classification number: G11C29/02 ,  G11C11/401 ,  G11C29/025

Abstract: A bridge defect detecting method performed in a semiconductor memory device that comprises a plurality of memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers connected to the bit lines, includes the operations of: enabling a first sense amplifier and a second sense amplifier; keeping the first sense amplifier in an enabled state and disabling the second sense amplifier; enabling the second sense amplifier, and detecting a bridge defect between the first memory cell and the second memory cell by reading data from a first memory cell of a first bit line connected to the first sense amplifier and a second memory cell of a second bit line connected to the second sense amplifier.

Abstract translation: 一种在半导体存储器件中执行的桥缺陷检测方法，包括布置在多个字线和多个位线之间的交叉处的多个存储器单元和连接到位线的多个读出放大器，包括以下操作： 实现第一读出放大器和第二读出放大器; 将所述第一读出放大器保持在使能状态并禁用所述第二读出放大器; 通过从连接到第一读出放大器的第一位线的第一存储器单元读取数据和第二位线的第二存储器单元来检测第一存储器单元和第二存储器单元之间的桥接缺陷， 连接到第二感测放大器。

公开(公告)号：US07038972B2

公开(公告)日：2006-05-02

申请号：US10793209

申请日：2004-03-04

Applicant: Sung-min Seo ,  Chi-wook Kim ,  Kyu-hyoun Kim

Inventor： Sung-min Seo ,  Chi-wook Kim ,  Kyu-hyoun Kim

IPC: G01C8/00

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.

Abstract translation: 提供了一种双倍数据速率（“DDR”）同步动态随机存取存储器（“SDRAM”）半导体器件，其防止当将数据写入DDR SDRAM半导体器件时从数据读取和写入DDR SDRAM半导体器件的数据之间的冲突 ，其包括延迟锁定环（“DLL”）电路，时钟信号控制单元，输出单元和输出控制单元，其中DLL电路补偿输入时钟信号的偏斜并产生输出时钟信号; 当读出存储在DDR SDRAM半导体器件中的数据时，时钟信号控制单元接收到激活的读取信号，当DLL电路对输入时钟信号执行锁定操作时激活的DLL锁定信号和输出时钟信号，并且输出 当读取信号或DLL锁定信号有效时，输出时钟信号; 输出单元缓冲存储在DDR SDRAM半导体器件中的数据，并将数据与从时钟信号控制单元输出的输出时钟信号同步地输出到DDR SDRAM半导体器件的外部; 并且输出控制单元接收从时钟信号控制单元输出的输出时钟信号和读取信号，并将读出的信号与从时钟信号控制单元输出的输出时钟信号同步输出到输出单元。

公开(公告)号：US06777987B2

公开(公告)日：2004-08-17

申请号：US10394682

申请日：2003-03-21

Applicant: Moo-sung Chae ,  Chi-wook Kim ,  Sung-min Seo

Inventor： Moo-sung Chae ,  Chi-wook Kim ,  Sung-min Seo

IPC: H03K300

CPC classification number: H03K5/14 ,  H03K5/12 ,  H03K19/01721 ,  H04L25/0288

Abstract: A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

Abstract translation: 信号线驱动电路包括反相缓冲器，脉冲发生器，第一信号缓冲器和第二信号缓冲器。 这里，反相缓冲器接收输入信号，并包括连接到信号线的输出端以驱动信号线。 脉冲发生器接收输入信号以产生脉冲信号。 第一信号缓冲器具有连接到脉冲发生器的输出端子的控制端子和连接到信号线的节点的输入/输出端子。 第一信号缓冲器响应于第一控制信号减小在信号线上传播的信号的上升转变时间。 第二信号缓冲器具有连接到脉冲发生器的输出端的控制端子和连接到信号线的节点的输入/输出端子。 第二信号缓冲器响应于第一控制信号减少在信号线上传播的信号的下降转变时间。

公开(公告)号：US06229756B1

公开(公告)日：2001-05-08

申请号：US09616380

申请日：2000-07-13

Applicant: Jin-Kyoung Jung ,  Chi-wook Kim

Inventor： Jin-Kyoung Jung ,  Chi-wook Kim

IPC: G11C800

CPC classification number: G11C7/1048 ,  G11C7/22

Abstract: A semiconductor memory device is provided that is capable of operating normally and having its operating speed unaffected, even when column address lines for transmitting column addresses are greatly loaded and even when the loads on the column address lines are simultaneously different from one another. The semiconductor memory device includes a column selection line driver for receiving decoded addresses and driving column selection lines of a memory cell array in response to a column selection line control signal, a column selection line control signal generator for receiving buffered column address data, and for generating the column selection line control signal in response to an internal clock signal and one of a first control signal and a second control signal, and a control signal generator for generating the first and second control signals in response to the internal clock signal, an externally-input column address strobe signal, and an externally-input write enable signal.

Abstract translation: 提供一种能够正常工作并且其运行速度不受影响的半导体存储器件，即使当用于传输列地址的列地址线被大量加载时，甚至当列地址线上的负载彼此同时不同时也是如此。 半导体存储器件包括：列选择线驱动器，用于响应于列选择线控制信号接收解码地址和驱动存储单元阵列的列选择线;列选择线控制信号发生器，用于接收缓冲列地址数据，以及用于 响应于内部时钟信号和第一控制信号和第二控制信号中的一个产生列选择线控制信号;以及控制信号发生器，用于响应于内部时钟信号产生第一和第二控制信号，外部 - 输入列地址选通信号和外部输入写使能信号。

公开(公告)号：US07692985B2

公开(公告)日：2010-04-06

申请号：US11775513

申请日：2007-07-10

Applicant: Soon-hong Ahn ,  Chi-wook Kim

Inventor： Soon-hong Ahn ,  Chi-wook Kim

IPC: G11C7/00

CPC classification number: G11C29/02 ,  G11C11/401 ,  G11C29/025

Abstract: A bridge defect detecting method performed in a semiconductor memory device that includes a plurality of memory cells arranged at intersections between a plurality of word lines and a plurality of bit lines and a plurality of sense amplifiers connected to the bit lines, includes the operations of: enabling a first sense amplifier and a second sense amplifier; keeping the first sense amplifier in an enabled state and disabling the second sense amplifier; enabling the second sense amplifier, and detecting a bridge defect between the first memory cell and the second memory cell by reading data from a first memory cell of a first bit line connected to the first sense amplifier and a second memory cell of a second bit line connected to the second sense amplifier.

Abstract translation: 一种在半导体存储器件中执行的桥缺陷检测方法，包括布置在多个字线和多个位线之间的交叉处的多个存储器单元和连接到位线的多个读出放大器的操作包括以下操作： 实现第一读出放大器和第二读出放大器; 将所述第一读出放大器保持在使能状态并禁用所述第二读出放大器; 通过从连接到第一读出放大器的第一位线的第一存储器单元读取数据和第二位线的第二存储器单元来检测第一存储器单元和第二存储器单元之间的桥接缺陷， 连接到第二感测放大器。