公开(公告)号：US6016551A

公开(公告)日：2000-01-18

申请号：US994303

申请日：1997-12-19

申请人： Gil Stoler ,  Tosaki Nakanishi

发明人： Gil Stoler ,  Tosaki Nakanishi

IPC分类号： G06F1/10 ,  G06F1/32 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F1/3237 ,  G06F1/10 ,  G06F1/3203 ,  G06F12/0831 ,  Y02B60/1221

摘要： A microprocessor having a cache memory unit, an execution unit, and clock masking circuitry is described. Both units are responsive to a clock signal that can be masked by the clock masking circuitry in order to reduce the power consumption of the microprocessor. Based on a signal that indicates a potential impending cache snoop, the clock masking circuitry can unmask the clock signal to the cache unit without unmasking the clock signal to the execution unit.

摘要翻译： 描述了具有高速缓冲存储器单元，执行单元和时钟屏蔽电路的微处理器。 两个单元响应于可被时钟屏​​蔽电路屏蔽的时钟信号，以便降低微处理器的功耗。 基于指示潜在的即将到来的高速缓存窥探的信号，时钟屏蔽电路可以将时钟信号屏蔽到高速缓存单元，而不会将时钟信号屏蔽到执行单元。

公开(公告)号：US07149227B2

公开(公告)日：2006-12-12

申请号：US10158476

申请日：2002-05-31

申请人： Gil Stoler ,  Diego Crupnicoff

发明人： Gil Stoler ,  Diego Crupnicoff

IPC分类号： H04B7/212 ,  H04J3/02

CPC分类号： G06F13/362 ,  H04L49/90

摘要： A method for allocating a processing resource among multiple inputs includes defining a sequence of multiplexing iterations, each such iteration including a first plurality of windows, each such window containing a second plurality of time slots. A respective weight is assigned to each of the inputs, and each of the inputs is allotted one of the time slots in each of a respective number of the windows in each of the iterations, the respective number being determined by the respective weight. Each of the inputs is then provided with access to the processing resource during the time slots allotted thereto.

公开(公告)号：US07245627B2

公开(公告)日：2007-07-17

申请号：US10127710

申请日：2002-04-23

申请人： Dror Goldenberg ,  Gil Bloch ,  Gil Stoler ,  Diego Crupnicoff ,  Michael Kagan

发明人： Dror Goldenberg ,  Gil Bloch ,  Gil Stoler ,  Diego Crupnicoff ,  Michael Kagan

IPC分类号： H04L12/56

CPC分类号： H04L47/10 ,  H04L47/125 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/351

摘要： A network interface device includes a fabric interface, adapted to exchange messages over a switch fabric with a plurality of host processors, the messages containing data, and a network interface, including one or more ports adapted to be coupled to a network external to the switch fabric. Message processing circuitry is coupled between the fabric interface and the network interface, so as to enable at least first and second host processors among the plurality of the host processors to use a single one of the ports substantially simultaneously so as to transmit and receive frames containing the data over the network.

摘要翻译： 网络接口设备包括：结构接口，适于通过交换结构与多个主处理器交换消息，所述消息包含数据，以及网络接口，包括一个或多个适于耦合到交换机外部的网络的端口 布。 消息处理电路耦合在结构接口和网络接口之间，以使多个主机处理器中的至少第一和第二主处理器基本上同时使用单个端口，以便发送和接收包含 网络上的数据。

公开(公告)号：US20140143487A1

公开(公告)日：2014-05-22

申请号：US13682781

申请日：2012-11-21

申请人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

摘要翻译： 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。

公开(公告)号：US08688911B1

公开(公告)日：2014-04-01

申请号：US12624213

申请日：2009-11-23

申请人： Tarek Rohana ,  Gil Stoler

发明人： Tarek Rohana ,  Gil Stoler

IPC分类号： G06F13/00

CPC分类号： G06F12/0888 ,  G06F12/0811 ,  G06F13/4027 ,  G06F13/4059

摘要： Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.

摘要翻译： 本公开的实施例提供一种芯片上的系统（SOC），其包括处理核心，该处理核心包括核心总线代理，总线接口单元（BIU）和将处理核心可操作地耦合到BIU的桥接模块，桥模块被配置为 通过绕过高速缓存，将信息从核心总线代理选择性地路由到高速缓存或BIU。 还描述和要求保护其他实施例。

公开(公告)号：US20100102869A1

公开(公告)日：2010-04-29

申请号：US12650125

申请日：2009-12-30

申请人： Gil Stoler ,  Ido Bourstein ,  Yiftach Banai

发明人： Gil Stoler ,  Ido Bourstein ,  Yiftach Banai

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222

摘要： An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

摘要翻译： 公开了用于产生一个或多个时钟信号的装置和方法。 基于模式信号和参考时钟信号产生时钟信号。 当参考时钟信号变为高电平时，输出第一模式信号的状态，并且当参考时钟信号变为低电平时，输出第二模式信号的状态。 根据参考时钟信号选择的第一和第二模式信号的连续状态提供所生成的时钟信号。

公开(公告)号：US5764932A

公开(公告)日：1998-06-09

申请号：US771529

申请日：1996-12-23

申请人： Simcha Gochman ,  Gil Stoler

发明人： Simcha Gochman ,  Gil Stoler

IPC分类号： G06F13/40 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： To improve computer performance, a second processor can be added to a computer system. However, when a second processor is added to a computer system, a dual processing protocol is required to ensure that the two processors share the computer resources. A robust dual processing protocol is introduced that allows two processors to share a single processor bus in an efficient manner. The dual processing protocol allows pipelined bus transfers wherein partial control of the bus is transferred. Furthermore, the dual processing protocol ensures cache coherency by having any modified cache line written back to main memory when a memory location represent by a modified internal cache line is accessed. The dual processing Protocol is designed to support a well defined fair and robust arbitration DP protocol between two processors that is independent of the core frequency and the bus fraction ratio. As such, the dual processing protocol is functional even if the two processors are running with different bus fractions ("heterogeneous DP"). The dual processing protocol is a Pure Bus Clock based protocol such that all the indications on the private interface are in pure bus-clock domain. This enables running in high core frequency, while not affecting the board related private interface parameters (such as flight time, valid/setup/hold of the processors private pins)--which makes the protocol robust and applicable to future upgrades/products with much higher internal frequencies.

摘要翻译： 为了提高计算机性能，可以将第二处理器添加到计算机系统。 然而，当将第二处理器添加到计算机系统时，需要双重处理协议以确保两个处理器共享计算机资源。 引入了强大的双处理协议，允许两个处理器以有效的方式共享单个处理器总线。 双处理协议允许其中传送总线的部分控制的流水线总线传输。 此外，当通过修改的内部高速缓存行表示的存储器位置被访问时，双重处理协议通过将任何经修改的高速缓存行写回到主存储器来确保高速缓存一致性。 双处理协议被设计为支持独立于核心频率和总线分数比的两个处理器之间的良好定义的公平和可靠的仲裁DP协议。 因此，即使两个处理器以不同的总线部分（“异种DP”）运行，双重处理协议也是有效的。 双处理协议是基于纯总线时钟的协议，使得私有接口上的所有指示都处于纯总线时钟域。 这使得能够以高核心频率运行，同时不影响板级相关的专用接口参数（如飞行时间，处理器专用引脚的有效/设置/保持），这使得协议稳健且适用于将来升级/产品高得多 内部频率。

公开(公告)号：US09141546B2

公开(公告)日：2015-09-22

申请号：US13682781

申请日：2012-11-21

申请人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

摘要翻译： 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。

公开(公告)号：US08499123B1

公开(公告)日：2013-07-30

申请号：US13357787

申请日：2012-01-25

申请人： Tarek Rohana ,  Gil Stoler

发明人： Tarek Rohana ,  Gil Stoler

IPC分类号： G06F13/00

CPC分类号： G06F12/0864 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/12

摘要： Embodiments of the present disclosure provide a command processing pipeline operatively coupled to an N-way cache and configured to process a sequence of cache commands. A way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit. In one embodiment, the command processing pipeline may be configured to receive a first cache command from one of the plurality of processing cores, select a way, from the N ways, as a potential eviction way, and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is (A). the hit way and/or the eviction way, or (B). neither the hit way nor the eviction way.

摘要翻译： 本公开的实施例提供了可操作地耦合到N路缓存并被配置为处理高速缓存命令序列的命令处理流水线。 高速缓存命令匹配的缓存的N种方式是高速缓存命令的命中方法，在缓存命令是命中的情况下。 在一个实施例中，命令处理流水线可以被配置为从多个处理核心之一接收第一高速缓存命令，从N个方式中选择一种方式作为潜在的驱逐方式，并至少部分基于 接收到的第一高速缓存命令，N个选择信号对应于N个方式，其中每个选择信号指示对应的方式是否是（A）。 命中方式和/或驱逐方式，或（B）。 既不是命中的方式也不是驱逐的方式。

公开(公告)号：US07932768B2

公开(公告)日：2011-04-26

申请号：US12650125

申请日：2009-12-30

申请人： Ido Bourstein ,  Yiftach Banai ,  Gil Stoler

发明人： Ido Bourstein ,  Yiftach Banai ,  Gil Stoler

IPC分类号： H03K3/00

CPC分类号： H03K5/135 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222

摘要： An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

摘要翻译： 公开了用于产生一个或多个时钟信号的装置和方法。 基于模式信号和参考时钟信号产生时钟信号。 当参考时钟信号变为高电平时，输出第一模式信号的状态，并且当参考时钟信号变为低电平时，输出第二模式信号的状态。 根据参考时钟信号选择的第一和第二模式信号的连续状态提供所生成的时钟信号。