公开(公告)号：US06233634B1

公开(公告)日：2001-05-15

申请号：US08697678

申请日：1996-08-17

申请人： Gordon R. Clark ,  George H. Myers ,  Louis R. Gagliardi ,  Siamak Tavallaei

发明人： Gordon R. Clark ,  George H. Myers ,  Louis R. Gagliardi ,  Siamak Tavallaei

IPC分类号： G06F1300

CPC分类号： G06F11/2294 ,  G06F11/0709 ,  G06F11/0748 ,  Y10T307/625 ,  Y10T307/729

摘要： A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols. The server controller snoops display data written from the host CPU to the video controller and mirrors the display data upon buffers within the server controller. Information within the buffers can be called upon by a remotely situated administrator regardless of whether server power is lost in the interim.

摘要翻译： 提供了一种通信系统，其中从主机CPU发送到视频控制器的视频屏幕序列可以被存储并且随后由位于远离主机CPU的终端检索。 主机CPU和视频控制器构成分布式计算系统中安排的服务器的一部分。 位于远程终端的管理员可以检索在服务器操作期间产生的选择视频屏幕，以确定有关服务器配置的信息以及服务器故障或未来故障的可能原因。 因此，视频屏幕的顺序表示存储在适于耦合到服务器扩展总线的服务器控制器上的视频屏幕改变。 视频屏幕更改表示在服务器故障之前或服务器重置后发生的视频屏幕更改的序列。 这些更改为位于远离服务器的管理员提供有益的信息，并允许管理员使用几种可能的通信协议与服务器进行通信。 服务器控制器将从主机CPU写入的数据显示给视频控制器，并在服务器控制器中的缓冲区上镜像显示数据。 缓冲区内的信息可由远程管理员调用，无论是否在过渡期间服务器功耗丢失。

公开(公告)号：US5864653A

公开(公告)日：1999-01-26

申请号：US775770

申请日：1996-12-31

申请人： Siamak Tavallaei ,  Louis R. Gagliardi ,  Joseph Peter Miller

发明人： Siamak Tavallaei ,  Louis R. Gagliardi ,  Joseph Peter Miller

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/2017 ,  G06F11/0745 ,  G06F11/0751

摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

公开(公告)号：US6105146A

公开(公告)日：2000-08-15

申请号：US226359

申请日：1999-01-06

申请人： Siamak Tavallaei ,  Louis R. Gagliardi ,  Joseph Peter Miller

发明人： Siamak Tavallaei ,  Louis R. Gagliardi ,  Joseph Peter Miller

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/2017 ,  G06F11/0745 ,  G06F11/0751

摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

摘要翻译： 用于主机服务器系统的系统管理模块（SMM）包括连接到系统管理本地总线的系统管理处理器（SMP）。 系统管理本地总线通过系统管理中心（SMC）连接到系统PCI总线。 SMC包括PCI总线的主要仲裁单元，还包括系统管理本地总线的仲裁器。 SMM包括连接到系统管理本地总线的视频控制器和键盘和鼠标控制器，以支持SMM的远程安装。 SMC包括监视PCI周期的逻辑，并在发生系统错误时发出错误信号。 SMC还通过屏蔽失败设备的请求，授权和中断线来隔离故障组件。 此外，如果提供备用组件，则SMC允许动态切换到备用组件。 除了检测错误和执行生存和维护操作之外，SMC通过支持主目标优先级确定来提高系统性能，从而更有效地仲裁系统总线（如PCI总线）的掌握。

公开(公告)号：US20110225353A1

公开(公告)日：2011-09-15

申请号：US13126141

申请日：2008-10-30

申请人： Robert C Elliott ,  Joseph E. Foster ,  Siamak Tavallaei

发明人： Robert C Elliott ,  Joseph E. Foster ,  Siamak Tavallaei

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0804 ,  G06F2212/2022

摘要： In at least some embodiments, a computing system includes a processor and a communication bus external to the processor. The computing system also includes a Redundant Array of Independent Disks (RAID) write cache sub-assembly coupled to the communication bus, the RAID write cache sub-assembly having non-volatile memory.

摘要翻译： 在至少一些实施例中，计算系统包括处理器和处理器外部的通信总线。 计算系统还包括耦合到通信总线的独立磁盘冗余阵列（RAID）写高速缓存子组件，该RAID写高速缓存子组件具有非易失性存储器。

公开(公告)号：US6134579A

公开(公告)日：2000-10-17

申请号：US911842

申请日：1997-08-15

申请人： Siamak Tavallaei ,  Jeffrey S. Autor

发明人： Siamak Tavallaei ,  Jeffrey S. Autor

IPC分类号： G06F15/177 ,  G06F9/46 ,  G06F13/362 ,  G06F9/00

CPC分类号： G06F9/52 ,  G06F2209/503

摘要： A computer system utilizing multiple processes includes a semaphore for controlling exclusive access of a single process to a selected resource. The semaphore is implemented in the system input/output and controlled, at least in part, by an application specific integrated circuit (ASIC). When a process is attempting to acquire an I/O resource, a read is sent to the semaphore. If the resource is available the semaphore will have a first value, and the semaphore will return that first value to the process indicating that the process has acquired the resource. The ASIC will then change the semaphore value to a second value. If the resource is not available the semaphore will have the second value, and the semaphore will return the second value to the process indicating that the resource is not available.

摘要翻译： 利用多个进程的计算机系统包括用于控制单个进程对所选资源的独占访问的信号量。 信号量在系统输入/输出中实现，至少部分地由专用集成电路（ASIC）控制。 当进程尝试获取I / O资源时，会将读取信息发送到信号量。 如果资源可用，则信号量将具有第一个值，并且信号量将返回该指示进程已获取资源的进程的第一个值。 然后，ASIC将信号量值更改为第二个值。 如果资源不可用，则信号量将具有第二个值，并且信号量将将第二个值返回给指示资源不可用的进程。

公开(公告)号：US20140211544A1

公开(公告)日：2014-07-31

申请号：US14342431

申请日：2011-09-02

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C5/04 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0047 ,  G11C2013/0073

摘要： Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a current across the memory cell to read a content of the memory cell. During a subsequent read cycle of the memory cell, a subsequent current is applied across the memory cell in the opposite direction to read the content of the memory cell.

摘要翻译： 公开了存储用于读取存储器单元的数据和方法的装置。 所公开的示例性方法涉及在存储器单元的读取周期期间，跨过存储器单元施加电流以读取存储器单元的内容。 在存储器单元的随后的读取周期期间，沿相反方向跨越存储器单元施加随后的电流以读取存储器单元的内容。

公开(公告)号：US07447818B2

公开(公告)日：2008-11-04

申请号：US10716144

申请日：2003-11-18

申请人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

发明人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

IPC分类号： G06F15/16 ,  G06F3/00

CPC分类号： G06F11/2294

摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

摘要翻译： 计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。 计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。 远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。 处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

公开(公告)号：US06792490B2

公开(公告)日：2004-09-14

申请号：US09991058

申请日：2001-11-16

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.

摘要翻译： 具有智能输入/输出架构的计算机系统具有用于隐藏外围设备的至少一部分的动态设备阻塞机制。 计算机系统包括用于执行主机操作系统的主机处理器，设置在主机总线上的主机处理器，经由主机到总线桥接器可操作地耦合到主机总线的输入/输出（I / O）总线， 以及可操作地连接到I / O总线的用于在由IOP资源控制的I / O事务中传送数据的多个外围设备。 多个I / O总线信号被提供给器件阻塞模块，用于确定哪个总线主机拥有I / O总线以便启动总线周期。 如果总线周期即将代表主处理器及其OS开始，则与选定的外围设备相关联的使能信号被否定，直到该周期完成。 另一方面，如果由IOP启动总线周期，则在交易持续时间内使能使能信号，否则，该信号保持在否定状态。

公开(公告)号：US06747563B2

公开(公告)日：2004-06-08

申请号：US10437567

申请日：2003-05-14

申请人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

发明人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

IPC分类号： G08B2300

CPC分类号： G06F13/4081 ,  G06F13/409

摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

摘要翻译： 一种基于处理器的设备，其具有通过杠杆系统固定在底盘内的多个存储器盒。 基于处理器的设备包括用于指示存储器系统操作条件的指示系统。 当从基于处理器的设备移除存储器盒时，每个存储器盒具有保护组件以保护存储器盒内的存储器元件。 基于处理器的设备是可操作的，使得可以从基于处理器的设备移除至少一个存储盒，而不影响基于处理器的设备的操作。

公开(公告)号：US06742066B2

公开(公告)日：2004-05-25

申请号：US10108106

申请日：2002-03-27

申请人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

发明人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

IPC分类号： G06F1516

CPC分类号： G06F11/2294

摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

摘要翻译： 计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。 计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。 远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。 处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。