公开(公告)号：US09438537B2

公开(公告)日：2016-09-06

申请号：US14406954

申请日：2012-07-03

申请人： Graham Edmiston ,  Hezi Rahamim ,  Amir Yosha

发明人： Graham Edmiston ,  Hezi Rahamim ,  Amir Yosha

IPC分类号： H04L12/28 ,  H04L12/861 ,  H04L12/721

CPC分类号： H04L49/90 ,  H04L45/66 ,  H04L49/9063

摘要： An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium.

摘要翻译： 电子设备根据定义数据分组的网络协议进行通信，例如EtherCAT。 该设备具有用于对输入数据分组执行输入控制并对输出数据分组执行输出控制的处理器，以及包括多用户存储器的共享FIFO缓冲器。 输入单元接收输入数据，检测相应数据分组的开始，将数据分组细分为连续分段，一段具有预定数量的数据字节，并且在下一分段被完全接收之前将该分段传送到FIFO缓冲器 。 处理器在输入控制中访问用于处理该段的多用户存储器，并且在输出控制中，在对应的输入数据分组被完全接收之前，启动输出输出分组。 输出单元从FIFO缓冲器传送段，并将段发送到通信介质。

公开(公告)号：US20150110126A1

公开(公告)日：2015-04-23

申请号：US14406954

申请日：2012-07-03

申请人： Graham Edmiston ,  Hezi Rahamim ,  Amir Yosha

发明人： Graham Edmiston ,  Hezi Rahamim ,  Amir Yosha

IPC分类号： H04L12/861 ,  H04L12/721

CPC分类号： H04L49/90 ,  H04L45/66 ,  H04L49/9063

摘要： An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium.

摘要翻译： 电子设备根据定义数据分组的网络协议进行通信，例如EtherCAT。 该设备具有用于对输入数据分组执行输入控制并对输出数据分组执行输出控制的处理器，以及包括多用户存储器的共享FIFO缓冲器。 输入单元接收输入数据，检测相应数据分组的开始，将数据分组细分为连续分段，一段具有预定数量的数据字节，并且在下一分段被完全接收之前将该分段传送到FIFO缓冲器 。 处理器在输入控制中访问用于处理该段的多用户存储器，并且在输出控制中，在对应的输入数据分组被完全接收之前，启动输出输出分组。 输出单元从FIFO缓冲器传送段，并将段发送到通信介质。

公开(公告)号：US20140233372A1

公开(公告)日：2014-08-21

申请号：US14348254

申请日：2011-11-04

申请人： Graham Edmiston ,  Hezi Rahamim

发明人： Graham Edmiston ,  Hezi Rahamim

IPC分类号： H04L12/24

CPC分类号： H04L41/0668 ,  H04L12/40019 ,  H04L12/40189 ,  H04L12/4035 ,  H04L12/437

摘要： A real-time distributed network module arranged to provide an interface between at least one master application and at least one real-time distributed network. The real-time distributed network module comprises a first communications component arranged to transmit and receive real-time distributed network data over at least a first real-time distributed network connection, at least one further communications component arranged to transmit and receive real-time distributed network data over at least one further real-time distributed network connection at least one master application interface component arranged to provide an interface to the at least one master application, and at least one configuration component arranged to perform mapping of communication channels between the first communications component, the at least one further communications component and the at least one master application interface component. The at least one configuration component is further arranged to perform dynamic remapping of the communication channels between the first communications component, the at least one further communications component and the at least one master application interface, upon detection of a link failure within the real-time distributed network.

摘要翻译： 布置成提供至少一个主应用与至少一个实时分布式网络之间的接口的实时分布式网络模块。 所述实时分布式网络模块包括被布置成通过至少第一实时分布式网络连接来发送和接收实时分布式网络数据的第一通信组件，布置成发送和接收实时分布式网络数据的至少一个另外的通信组件 通过至少一个另外的实时分布式网络连接的网络数据，布置成提供到所述至少一个主应用的接口的至少一个主应用接口组件以及被配置为执行第一通信之间的通信信道的映射的至少一个配置组件 组件，所述至少一个另外的通信组件和所述至少一个主应用程序接口组件。 所述至少一个配置组件还被布置成在检测到实时内的链路故障时，在第一通信组件，所述至少一个另外的通信组件和至少一个主应用接口之间执行通信信道的动态重新映射 分布式网络。

公开(公告)号：US09674032B2

公开(公告)日：2017-06-06

申请号：US14348254

申请日：2011-11-04

申请人： Graham Edmiston ,  Hezi Rahamim

发明人： Graham Edmiston ,  Hezi Rahamim

IPC分类号： H04L12/24 ,  H04L12/40 ,  H04L12/403 ,  H04L12/437

CPC分类号： H04L41/0668 ,  H04L12/40019 ,  H04L12/40189 ,  H04L12/4035 ,  H04L12/437

摘要： A real-time distributed network module arranged to provide an interface between at least one master application and at least one real-time distributed network. The real-time distributed network module comprises a first communications component arranged to transmit and receive real-time distributed network data over at least a first real-time distributed network connection, at least one further communications component arranged to transmit and receive real-time distributed network data over at least one further real-time distributed network connection at least one master application interface component arranged to provide an interface to the at least one master application, and at least one configuration component arranged to perform mapping of communication channels between the first communications component, the at least one further communications component and the at least one master application interface component. The at least one configuration component is further arranged to perform dynamic remapping of the communication channels between the first communications component, the at least one further communications component and the at least one master application interface, upon detection of a link failure within the real-time distributed network.

公开(公告)号：US09450894B2

公开(公告)日：2016-09-20

申请号：US14125203

申请日：2011-06-15

申请人： Graham Edmiston

发明人： Graham Edmiston

IPC分类号： H04L12/28 ,  H04L12/861 ,  H04L12/54 ,  H04L12/721 ,  H04L12/773

CPC分类号： H04L49/9057 ,  H04L12/56 ,  H04L45/40 ,  H04L45/60

摘要： An integrated circuit device includes a cut-through forwarding module. The cut-through forwarding module includes at least one receiver component arranged to receive data to be forwarded, and at least one transmitter component arranged to transmit data stored within at least one transmitter buffer thereof. The cut-through forwarding module further includes at least one delimiter component arranged to trigger a transmission of frame data within the at least one transmitter buffer, upon receipt of a first number elements of a respective data frame by the at least one receiver component, the first number of data elements comprising a first predefined integer value.

摘要翻译： 集成电路装置包括一个直通转发模块。 切入转发模块包括布置成接收要转发的数据的至少一个接收器组件，以及布置成发送存储在其至少一个发射机缓冲器内的数据的至少一个发射机组件。 直通转发模块还包括至少一个限定器组件，其被布置成在由至少一个接收器组件接收到相应数据帧的第一数字元素时触发至少一个发射器缓冲器内的帧数据的传输， 第一数量的数据元素包括第一预定整数值。

公开(公告)号：US20150117446A1

公开(公告)日：2015-04-30

申请号：US14395718

申请日：2012-04-26

申请人： Graham Edmiston

发明人： Graham Edmiston

IPC分类号： H04L12/947

CPC分类号： H04L49/251 ,  H04L45/40 ,  H04L49/1546 ,  H04L69/12

摘要： The disclosure relates to cut-through forwarding module, an integrated circuit, a semiconductor device and a method of receiving and transmitting data frames in a cut-through forwarding mode. The cut-through forwarding module processes received data frames in data blocks. The module comprises a pre-loading unit for storing a first data block of a received data frame. The stored first data block may be pre-loaded by the pre-loading unit in a transmitter unit before a receiver unit receives a subsequent data frame. The processing unit controls the transfer of a first data block to the pre-loading unit and controls the use of a pre-loaded data block as a first data block of a data frame to be transmitted.

摘要翻译： 本公开涉及直通转发模块，集成电路，半导体装置和以切入转发模式接收和发送数据帧的方法。 直通转发模块处理数据块中的接收数据帧。 该模块包括用于存储接收到的数据帧的第一数据块的预加载单元。 存储的第一数据块可以在接收机单元接收到随后的数据帧之前由预加载单元在发射机单元中预加载。 处理单元控制第一数据块到预加载单元的传送，并且控制使用预加载的数据块作为要发送的数据帧的第一数据块。

公开(公告)号：US20140029625A1

公开(公告)日：2014-01-30

申请号：US14007861

申请日：2011-04-20

申请人： Graham Edmiston

发明人： Graham Edmiston

IPC分类号： H04L12/863

CPC分类号： H04L47/623 ,  H04L45/40 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/257

摘要： An integrated circuit device comprising at least one cut-through forwarding module. The cut-through forwarding module comprises at least one receiver component arranged to receive data to be forwarded, and to generate a request for transmission of a block of data upon receipt thereof, and at least one controller unit arranged to execute at least one thread for processing requests generated by the at least one receiver component. The at least one controller unit is arranged to set a priority context for the at least one thread, and to schedule an execution of the at least one thread based at least partly on the priority context therefor.

摘要翻译： 一种包括至少一个直通转发模块的集成电路装置。 切入转发模块包括至少一个接收器组件，被布置为接收要转发的数据，并且在接收到数据块时产生对数据块的传输的请求，以及至少一个控制器单元，被配置为执行至少一个线程 处理由所述至少一个接收器组件产生的请求。 所述至少一个控制器单元被布置为至少部分地基于所述优先级上下文来设置所述至少一个线程的优先级上下文，并且调度所述至少一个线程的执行。

公开(公告)号：US09952922B2

公开(公告)日：2018-04-24

申请号：US14899595

申请日：2013-07-18

申请人： Graham Edmiston ,  Alan Devine ,  David McMenamin ,  Andrew Roberston ,  James Andrew Collier Scobie

发明人： Graham Edmiston ,  Alan Devine ,  David McMenamin ,  Andrew Roberston ,  James Andrew Collier Scobie

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/28

CPC分类号： G06F11/079 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/28

摘要： Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

公开(公告)号：US09817784B2

公开(公告)日：2017-11-14

申请号：US14778126

申请日：2013-03-22

申请人： Graham Edmiston

发明人： Graham Edmiston

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/362

CPC分类号： G06F13/4072 ,  G06F13/362 ,  G06F13/382

摘要： A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. One transmitter is a master transmitter that issues a request to the processor to provide a data block when the transmitter buffer of the master transmitter has free space to store a data block. The processor is arranged to copy at least one data block of data stored in an external memory from the external memory to respective positions in a local buffer. The processor is arranged to, in accordance with a predefined sequence, sequentially initiate transfer of the data block from the respective position of the data block in the local buffer to the transmitter buffers of the at least two transmitters in response to a request from the master transmitter to provide a data block.

公开(公告)号：US20160292014A1

公开(公告)日：2016-10-06

申请号：US14672596

申请日：2015-03-30

申请人： Graham Edmiston

发明人： Graham Edmiston

IPC分类号： G06F9/52 ,  G06F9/48

CPC分类号： G06F9/52 ,  G06F9/38 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Apparatuses, methods, and systems are configured to perform unambiguous parameter sampling in a heterogeneous multi-core or multi-threaded environment by masking one or more thread requests; and, in response to bus activity ceasing for the one or more masked thread requests and completing any routine being processed for the one or more masked threads, processing a command by executing at least one of a command routine or a command thread, wherein the command routine or the command thread reads the parameter using thread atomicity with deterministic synchronization. One or more thread requests may be selected for masking by monitoring thread activity for each of a plurality of threads.

摘要翻译： 设备，方法和系统被配置为通过掩蔽一个或多个线程请求来在异构多核或多线程环境中执行明确的参数采样; 并且响应于总线活动停止一个或多个屏蔽的线程请求并且完成针对一个或多个被屏蔽的线程正在处理的任何例程，通过执行命令例程或命令线程中的至少一个来处理命令，其中命令 例程或命令线程使用确定性同步的线程原子读取参数。 可以通过监视多个线程中的每个线程的线程活动来选择一个或多个线程请求以进行掩蔽。