Method to Reduce Charge Buildup During High Aspect Ratio Contact Etch
    1.
    发明申请
    Method to Reduce Charge Buildup During High Aspect Ratio Contact Etch 有权
    在高宽比接触蚀刻时减少电荷积累的方法

    公开(公告)号:US20110250759A1

    公开(公告)日:2011-10-13

    申请号:US13164970

    申请日:2011-06-21

    IPC分类号: H01L21/3065

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Method to reduce charge buildup during high aspect ratio contact etch
    2.
    发明授权
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号:US08673787B2

    公开(公告)日:2014-03-18

    申请号:US13164970

    申请日:2011-06-21

    IPC分类号: H01L21/302

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过将在蚀刻过程中沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Method to reduce charge buildup during high aspect ratio contact etch
    3.
    发明授权
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号:US07344975B2

    公开(公告)日:2008-03-18

    申请号:US11213283

    申请日:2005-08-26

    IPC分类号: H01L21/4763

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Method to reduce charge buildup during high aspect ratio contact etch
    4.
    发明授权
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号:US07985692B2

    公开(公告)日:2011-07-26

    申请号:US12018254

    申请日:2008-01-23

    IPC分类号: H01L21/302

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    METHOD TO REDUCE CHARGE BUILDUP DURING HIGH ASPECT RATIO CONTACT ETCH
    5.
    发明申请
    METHOD TO REDUCE CHARGE BUILDUP DURING HIGH ASPECT RATIO CONTACT ETCH 有权
    在高比例接触蚀刻期间减少充电建筑物的方法

    公开(公告)号:US20080128389A1

    公开(公告)日:2008-06-05

    申请号:US12018254

    申请日:2008-01-23

    IPC分类号: B44C1/22

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Methods of etching features into substrates
    6.
    发明授权
    Methods of etching features into substrates 有权
    将特征蚀刻到基底中的方法

    公开(公告)号:US07857982B2

    公开(公告)日:2010-12-28

    申请号:US11185229

    申请日:2005-07-19

    IPC分类号: H01L21/302

    摘要: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.

    摘要翻译: 本发明包括将特征蚀刻到基底中的方法。 在待蚀刻的基板的材料上形成多个硬掩模层。 在这样的层中形成特征图案。 使用其中具有特征图案的硬掩模层作为掩模,将特征部分地蚀刻到基底材料中。 在部分蚀刻之后,相对于衬底材料选择性蚀刻至少一个硬掩模层,并保留硬掩模层。 在蚀刻至少一个硬掩模层之后,使用至少最内侧的硬掩模层作为掩模将特征进一步蚀刻到基底材料中。 在进一步蚀刻之后,从衬底去除最内层的硬掩模层和剩余的硬掩模层,并且将特征的至少一部分结合到集成电路中。

    Method to reduce charge buildup during high aspect ratio contact etch
    7.
    发明申请
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号:US20070049018A1

    公开(公告)日:2007-03-01

    申请号:US11213283

    申请日:2005-08-26

    IPC分类号: H01L21/44 H01L21/302

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Methods of etching features into substrates
    8.
    发明申请
    Methods of etching features into substrates 有权
    将特征蚀刻到基底中的方法

    公开(公告)号:US20070020936A1

    公开(公告)日:2007-01-25

    申请号:US11185229

    申请日:2005-07-19

    IPC分类号: C23F1/00 H01L21/302

    摘要: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.

    摘要翻译: 本发明包括将特征蚀刻到基底中的方法。 在待蚀刻的基板的材料上形成多个硬掩模层。 在这样的层中形成特征图案。 使用其中具有特征图案的硬掩模层作为掩模,将特征部分地蚀刻到基底材料中。 在部分蚀刻之后,相对于衬底材料选择性蚀刻至少一个硬掩模层,并保留硬掩模层。 在蚀刻至少一个硬掩模层之后,使用至少最内侧的硬掩模层作为掩模将特征进一步蚀刻到基底材料中。 在进一步蚀刻之后,从衬底去除最内层的硬掩模层和剩余的硬掩模层,并且将特征的至少一部分结合到集成电路中。