Method to reduce charge buildup during high aspect ratio contact etch
    1.
    发明申请
    Method to reduce charge buildup during high aspect ratio contact etch 有权
    在高纵横比接触蚀刻期间减少电荷积累的方法

    公开(公告)号:US20070049018A1

    公开(公告)日:2007-03-01

    申请号:US11213283

    申请日:2005-08-26

    IPC分类号: H01L21/44 H01L21/302

    摘要: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

    摘要翻译: 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积,以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

    Controlled linewidth reduction during gate pattern formation using a
spin-on barc
    2.
    发明授权
    Controlled linewidth reduction during gate pattern formation using a spin-on barc 失效
    使用旋转棒条在栅极图案形成期间的受控线宽减小

    公开(公告)号:US5965461A

    公开(公告)日:1999-10-12

    申请号:US905109

    申请日:1997-08-01

    摘要: A gate is formed by depositing a gate conductive layer over a substrate layer, depositing an organic spin-on bottom anti-reflective coating (BARC) over the gate conductive layer, and forming a resist mask on the BARC. Next, the resist mask is controllably etched to further reduce the critical dimensions of gate pattern formed therein, and then the gate is formed by etching the gate conductive layer using the reduced size resist mask.

    摘要翻译: 通过在衬底层上沉积栅极导电层,在栅极导电层上沉积有机旋涂底部抗反射涂层(BARC)并在BARC上形成抗蚀剂掩模来形成栅极。 接下来,可控地蚀刻抗蚀剂掩模,以进一步减小其中形成的栅极图案的临界尺寸,然后通过使用减小尺寸的抗蚀剂掩模蚀刻栅极导电层来形成栅极。

    Controlled linewidth reduction during gate pattern formation using an
SiON BARC
    3.
    发明授权
    Controlled linewidth reduction during gate pattern formation using an SiON BARC 失效
    使用SiON BARC在栅极图案形成期间的受控线宽减小

    公开(公告)号:US6107172A

    公开(公告)日:2000-08-22

    申请号:US905104

    申请日:1997-08-01

    摘要: A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

    摘要翻译: 通过产生晶片堆叠形成栅极,该晶片堆叠包括在衬底层上的栅极导电层,在导电层上方沉积SiOxNy层以充当底部抗反射涂层(BARC),并在SiO x N y上形成抗蚀剂掩模 层。 接下来,抗蚀剂掩模被各向同性地蚀刻以进一步减小在其中形成的栅极图案的临界尺寸,然后蚀刻下面的BARC和晶片叠层以在导电层外形成栅极。

    Implanted photoresist to reduce etch erosion during the formation of a semiconductor device
    4.
    发明申请
    Implanted photoresist to reduce etch erosion during the formation of a semiconductor device 审中-公开
    植入光致抗蚀剂,以减少形成半导体器件期间的蚀刻侵蚀

    公开(公告)号:US20060043536A1

    公开(公告)日:2006-03-02

    申请号:US10931655

    申请日:2004-08-31

    IPC分类号: H01L23/58 H01L21/461

    摘要: A method for forming a semiconductor device comprises forming a layer to be etched, and forming a patterned photoresist layer over the layer to be etched. The patterned photoresist layer is treated prior to etching, for example by implantation with argon or nitrogen. This treatment reduces the volume of the photoresist, possibly by densifying the layer, which results in the photoresist layer being more resistant to an etch and decreasing the size of the feature to be formed. After treating the photoresist layer, the layer to be etched is exposed to an etchant.

    摘要翻译: 一种用于形成半导体器件的方法包括形成待蚀刻的层,并在待蚀刻的层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层在蚀刻之前被处理,例如通过用氩或氮注入。 这种处理可能通过致密化该层来降低光致抗蚀剂的体积,这导致光致抗蚀剂层更能抵抗蚀刻并且减小要形成的特征的尺寸。 在处理光致抗蚀剂层之后,将要蚀刻的层暴露于蚀刻剂。