公开(公告)号：US08686487B2

公开(公告)日：2014-04-01

申请号：US11763335

申请日：2007-06-14

申请人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

发明人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

摘要： Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

摘要翻译： 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US20080308858A1

公开(公告)日：2008-12-18

申请号：US11763335

申请日：2007-06-14

申请人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

发明人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

摘要： Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

摘要翻译： 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US08076717B2

公开(公告)日：2011-12-13

申请号：US12469433

申请日：2009-05-20

申请人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

发明人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的第二硅化物层。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US08253191B2

公开(公告)日：2012-08-28

申请号：US13291591

申请日：2011-11-08

申请人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

发明人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的第二硅化物层。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US20120049272A1

公开(公告)日：2012-03-01

申请号：US13291591

申请日：2011-11-08

申请人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

发明人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的第二硅化物层。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US20100295119A1

公开(公告)日：2010-11-25

申请号：US12469433

申请日：2009-05-20

申请人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

发明人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的第二硅化物层。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US20070018228A1

公开(公告)日：2007-01-25

申请号：US11185320

申请日：2005-07-20

申请人： Gurtej Sandhu ,  Chandra Mouli

发明人： Gurtej Sandhu ,  Chandra Mouli

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  B82Y10/00 ,  G11C13/025 ,  G11C16/0416 ,  G11C16/0483 ,  G11C2213/17 ,  G11C2213/75 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/511 ,  H01L29/7881 ,  H01L51/0048

摘要： Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated near the source/drain regions. For some embodiments, the tunnel dielectric layer may adjoin the substrate in at least a portion of the channel region.

摘要翻译： 具有插入在基板和隧道介电层之间的碳纳米管的浮栅存储器单元有助于将电荷弹入注入浮栅。 碳纳米管可以延伸穿过整个通道区域或沟道区域的一部分。 对于一些实施例，碳纳米管可以集中在源极/漏极区附近。 对于一些实施例，隧道介电层可以在沟道区域的至少一部分中与衬底相邻。

公开(公告)号：US20060286747A1

公开(公告)日：2006-12-21

申请号：US11155197

申请日：2005-06-17

申请人： Chandra Mouli ,  Gurtej Sandhu

发明人： Chandra Mouli ,  Gurtej Sandhu

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7883 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/66825

摘要： Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.

公开(公告)号：US20060040466A1

公开(公告)日：2006-02-23

申请号：US10925079

申请日：2004-08-23

申请人： Gurtej Sandhu ,  Chandra Mouli

发明人： Gurtej Sandhu ,  Chandra Mouli

IPC分类号： H01L21/76

CPC分类号： H01L27/10888 ,  H01L21/26533 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0214 ,  H01L27/10855 ,  H01L27/10873 ,  H01L28/40 ,  H01L29/0653 ,  H01L29/1083

摘要： This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion implantion is conducted into semiconductive material of the substrate to form a buried region within active area of the substrate. The buried region has a first edge received proximate an edge of the trench isolation region. Using the trench isolation mask, etching is conducted into semiconductive material of the substrate to form an isolation trench. After the ion implantation and after forming the isolation trench, insulative material is formed within the buried region and insulative material is deposited to within the isolation trench. The insulative material received within the isolation trench joins with the insulative material formed within the buried region.

摘要翻译： 本发明包括形成集成电路的方法，并且包括DRAM电路存储单元。 在一个实施方案中，形成集成电路的方法包括在半导体衬底上形成沟槽隔离掩模。 沟槽隔离掩模限定有源区域区域和沟槽隔离区域。 将离子注入导入衬底的半导体材料中以在衬底的有效区域内形成掩埋区域。 掩埋区域具有靠近沟槽隔离区域的边缘接收的第一边缘。 使用沟槽隔离掩模，蚀刻进入衬底的半导体材料以形成隔离沟槽。 在离子注入之后并且在形成隔离沟槽之后，在掩埋区域内形成绝缘材料，并且将绝缘材料沉积到隔离沟槽内。 接收在隔离沟槽内的绝缘材料与形成在掩埋区域内的绝缘材料接合。

公开(公告)号：US20060040455A1

公开(公告)日：2006-02-23

申请号：US11255613

申请日：2005-10-21

申请人： Gurtej Sandhu ,  Chandra Mouli

发明人： Gurtej Sandhu ,  Chandra Mouli

IPC分类号： H01L21/331

CPC分类号： H01L27/10888 ,  H01L21/26533 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0214 ,  H01L27/10855 ,  H01L27/10873 ,  H01L28/40 ,  H01L29/0653 ,  H01L29/1083

摘要： This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion implantion is conducted into semiconductive material of the substrate to form a buried region within active area of the substrate. The buried region has a first edge received proximate an edge of the trench isolation region. Using the trench isolation mask, etching is conducted into semiconductive material of the substrate to form an isolation trench. After the ion implantation and after forming the isolation trench, insulative material is formed within the buried region and insulative material is deposited to within the isolation trench. The insulative material received within the isolation trench joins with the insulative material formed within the buried region.