公开(公告)号：US07112506B2

公开(公告)日：2006-09-26

申请号：US10878747

申请日：2004-06-28

申请人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

发明人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

IPC分类号： H01L21/20

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/75

摘要： Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.

摘要翻译： 公开了一种形成半导体器件的电容器的方法。 蚀刻停止层，第一氧化物层和第二氧化物层依次沉积在基板的绝缘中间层上。 形成了绝缘中间层的插塞之上的蚀刻停止层的部分露出的接触孔。 接触孔由具有比第二氧化物层高的第一氧化物层的蚀刻选择性的清洗溶液清洁，从而扩大接触孔的下部。 在接触孔和第二氧化物层的表面上形成间隔氮化物层。 去除位于第二氧化物层上和插塞上方的间隔氮化物层的一部分以及位于插塞上的蚀刻停止层的部分。 在间隔氮化物层段上形成双重多晶硅层。

公开(公告)号：US06893914B2

公开(公告)日：2005-05-17

申请号：US10603895

申请日：2003-06-25

申请人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

发明人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

IPC分类号： H01L21/308 ,  H01L21/304 ,  H01L21/306 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L21/31133 ,  H01L21/3165 ,  H01L27/10814

摘要： A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.

摘要翻译： 这里描述了一种用于制造半导体器件的方法，其中通过在电池区域中的氧化膜的湿蚀刻工艺中选择性地蚀刻在电池区中用于防止电池之间的桥接的氧化膜形成圆柱形电容器。 通过用光致抗蚀剂膜覆盖外围电路区域并选择性地蚀刻电池区域中的氧化膜，使形成在电池区域中的层间绝缘膜与形成在外围电路区域中的层间绝缘膜之间的阶梯差被最小化，以形成圆柱形 电容器，从而简化制造过程。 此外，通过使用单个湿站进行简单的湿式蚀刻处理来防止电池之间的桥接，而不进行用于去除氧化膜和光致抗蚀剂膜图案的单独的干蚀刻工艺，从而提高器件的产量。

公开(公告)号：US07588996B2

公开(公告)日：2009-09-15

申请号：US11770983

申请日：2007-06-29

申请人： Hyo Geun Yoon ,  Woo Jin Kim ,  Dong Joo Kim ,  Ji Yong Park ,  Yong Soo Jung ,  Geun Min Choi ,  Young Wok Song ,  Sang Hyun Lee

发明人： Hyo Geun Yoon ,  Woo Jin Kim ,  Dong Joo Kim ,  Ji Yong Park ,  Yong Soo Jung ,  Geun Min Choi ,  Young Wok Song ,  Sang Hyun Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/3086 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31155

摘要： An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.

摘要翻译： 氧化物图案形成方法包括在半导体衬底上形成氧化物层，在给定区域中的氧化物层上注入不少于1.0×10 16原子/ cm 2的硼离子，并在剩余的区域中湿法蚀刻氧化物层，其中硼 离子不被植入。

公开(公告)号：US20080132073A1

公开(公告)日：2008-06-05

申请号：US11770983

申请日：2007-06-29

申请人： Hyo Geun Yoon ,  Woo Jin Kim ,  Dong Joo Kim ,  Ji Yong Park ,  Yong Soo Jung ,  Geun Min Choi ,  Young Wok Song ,  Sang Hyun Lee

发明人： Hyo Geun Yoon ,  Woo Jin Kim ,  Dong Joo Kim ,  Ji Yong Park ,  Yong Soo Jung ,  Geun Min Choi ,  Young Wok Song ,  Sang Hyun Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31155

摘要： An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.

摘要翻译： 氧化物图案形成方法包括在半导体衬底上形成氧化物层，在给定的氧化物层中将不少于1.0×10 16原子/ cm 2的硼离子注入到氧化物层上 区域，并且在没有植入硼离子的剩余区域中湿法蚀刻氧化物层。

公开(公告)号：US20110212610A1

公开(公告)日：2011-09-01

申请号：US13038284

申请日：2011-03-01

申请人： Gyu Hyun Kim ,  Geun Min Choi ,  Baik Il Choi ,  Dong Joo Kim ,  Ji Hye Han

发明人： Gyu Hyun Kim ,  Geun Min Choi ,  Baik Il Choi ,  Dong Joo Kim ,  Ji Hye Han

IPC分类号： H01L21/20

CPC分类号： H01L21/823842

摘要： Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions.

公开(公告)号：US20070148848A1

公开(公告)日：2007-06-28

申请号：US11614975

申请日：2006-12-22

申请人： Gyu Hyun Kim ,  Geun Min Choi ,  Baik II Choi ,  Dong Joo Kim ,  Ji Hye Han

发明人： Gyu Hyun Kim ,  Geun Min Choi ,  Baik II Choi ,  Dong Joo Kim ,  Ji Hye Han

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to first wet cleaning, second wet cleaning and dry cleaning.

摘要翻译： 本文公开了一种用于形成半导体器件的双栅极的方法。 该方法包括以下步骤：分别在半导体衬底的第一区域和第二区域上形成掺杂有p型杂质离子的第一多晶硅层和掺杂n型杂质离子的第二多晶硅层， 的第一和第二多晶硅层进行第一次湿式清洗，第二次湿式清洗和干洗。

公开(公告)号：US07282421B2

公开(公告)日：2007-10-16

申请号：US10998809

申请日：2004-11-30

申请人： Yong Soo Choi ,  Hyuk Kwon ,  Sang Hwa Lee ,  Geun Min Choi ,  Yong Wook Song ,  Gyu Han Yoon

发明人： Yong Soo Choi ,  Hyuk Kwon ,  Sang Hwa Lee ,  Geun Min Choi ,  Yong Wook Song ,  Gyu Han Yoon

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76224 ,  Y10S438/975

摘要： A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and forming a dummy active region pattern substantially adjacent to a vernier key pattern in the scribe lane during formation of the vernier key pattern, wherein the dummy active region pattern is spaced apart from the vernier key pattern by a known distance. Preferably, the active region pattern and the dummy active region pattern are formed prior to the STI CMP process.

摘要翻译： 提供了一种用于减小浅沟槽隔离（STI）CMP工艺中的氮化物层的厚度变化的方法，该方法包括在形成器件隔离膜的划线的对准键区域中形成有源区域图案 ISO水平，并且在形成游标键图案期间形成与划线中的游标键图案基本相邻的虚拟有源区域图案，其中虚拟有源区域图案与游标键图案间隔已知距离。 优选地，在STI CMP处理之前形成有源区图案和伪有源区图案。