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公开(公告)号：US20110225465A1
公开(公告)日：2011-09-15
申请号：US12723743
申请日：2010-03-15
申请人： H. Lee Blackmon , Ronald E. Freking , Ryan S. Haraden , Joseph A. Kirscht , Elizabeth A. McGlone
发明人： H. Lee Blackmon , Ronald E. Freking , Ryan S. Haraden , Joseph A. Kirscht , Elizabeth A. McGlone
CPC分类号： G06F11/073 , G06F11/076 , G11C11/406 , G11C11/40611
摘要： Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules.
摘要翻译： 公开了一种在存储器控制器上管理存储器刷新的系统和方法。 一种方法包括在存储器控制器设备处确定存储器控制器端口和存储器重新启动设备之间的传输错误的数量超过错误阈值。 该方法可以包括启动存储器控制器端口和存储器重新驱动设备之间的第一链路再培训过程。 该方法还可以包括将与存储器重新启动设备相关联的一个或多个动态随机存取存储器模块置于自刷新模式中。 该方法还可以包括在链路重新训练过程完成之后从自刷新模式移除一个或多个动态随机存取存储器模块。 该方法还可以包括实现一个或多个动态随机存取存储器模块的重叠刷新。
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公开(公告)号：US08397100B2
公开(公告)日：2013-03-12
申请号：US12723743
申请日：2010-03-15
申请人： H. Lee Blackmon , Ronald E. Freking , Ryan S. Haraden , Joseph A. Kirscht , Elizabeth A. McGlone
发明人： H. Lee Blackmon , Ronald E. Freking , Ryan S. Haraden , Joseph A. Kirscht , Elizabeth A. McGlone
IPC分类号： G06F11/07
CPC分类号： G06F11/073 , G06F11/076 , G11C11/406 , G11C11/40611
摘要： Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules.
摘要翻译： 公开了一种在存储器控制器上管理存储器刷新的系统和方法。 一种方法包括在存储器控制器设备处确定存储器控制器端口和存储器重新启动设备之间的传输错误的数量超过错误阈值。 该方法可以包括启动存储器控制器端口和存储器重新驱动设备之间的第一链路再培训过程。 该方法还可以包括将与存储器重新启动设备相关联的一个或多个动态随机存取存储器模块置于自刷新模式中。 该方法还可以包括在链路重新训练过程完成之后从自刷新模式移除一个或多个动态随机存取存储器模块。 该方法还可以包括实现一个或多个动态随机存取存储器模块的重叠刷新。
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公开(公告)号：US20090094385A1
公开(公告)日：2009-04-09
申请号：US11868603
申请日：2007-10-08
IPC分类号： G06F13/16
CPC分类号： G06F9/3855 , G06F9/3857
摘要： A technique for handling commands includes assigning respective first tags to ordered commands included in an ordered command stream. Respective second tags are then assigned to subsequent commands that follow an initial command (included in the ordered commands). Each of the respective second tags correspond to one the respective first tags that is associated with an immediate previous one of the ordered commands. The initial command is sent to an execution engine in a first cycle. At least one of the subsequent commands is sent to the execution engine prior to completion of execution of the initial command.
摘要翻译： 用于处理命令的技术包括将相应的第一标签分配给包括在有序命令流中的有序命令。 然后将相应的第二个标签分配给遵循初始命令（包括在有序命令中）的后续命令。 每个相应的第二标签对应于与紧接着的先前的一个有序命令相关联的相应的第一标签中的一个。 初始命令在第一个周期内发送到执行引擎。 在完成初始命令的执行之前，至少一个随后的命令被发送到执行引擎。
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4.发明申请Method and Apparatus for Enabling Virtual Channels Within A Peripheral Component Interconnect (PCI) Express Bus 审中-公开用于在外围组件互连（PCI）Express Bus中启用虚拟通道的方法和装置公开(公告)号：US20080052431A1
公开(公告)日：2008-02-28
申请号：US11466136
申请日：2006-08-22
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A method for enabling virtual channels within a Peripheral Component Interconnect (PCI) Express chipset is disclosed. A first determination is made as to whether or not bifurcation is enabled on a PCI Express chipset. If bifurcation is enabled, a second determination is made as to whether or not all resources associated with the bifurcation are being utilized. If all resources associated with the bifurcation are not being utilized, the PCI Express configuration space is changed to provide support for virtual channels by mapping a set of virtual channels to available resources associated with the bifurcation.
摘要翻译： 公开了一种用于在外围组件互连（PCI）Express芯片组内启用虚拟通道的方法。 首先确定在PCI Express芯片组上是否启用分岔。 如果分支被启用，则进行关于是否正在利用与分岔相关联的所有资源的第二确定。 如果没有利用与分叉相关联的所有资源，则通过将一组虚拟通道映射到与分岔相关联的可用资源，更改PCI Express配置空间以提供对虚拟通道的支持。
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公开(公告)号：US09043526B2
公开(公告)日：2015-05-26
申请号：US13528146
申请日：2012-06-20
IPC分类号： G06F13/40
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.
摘要翻译： 每个PCIe设备可以包括支持多个不同通道配置的媒体访问控制（MAC）接口和物理（PHY）接口。 这些接口可以包括支持1×32,2×16,4×8,8×4,16×2和32×1通信的硬件模块。 代替使用专用迹线将MAC接口中的每个硬件模块物理连接到PHY接口中的相应硬件模块，该设备可以包括两个总线控制器，其仲裁哪些硬件模块连接到耦合两个接口的内部总线。 当需要不同的通道配置时，总线控制器将相应的硬件模块耦合到内部总线。 以这种方式，不同的通道配置与其他通道配置共享总线的相同通道（和线）。 因此，共享总线仅需要包括足够的通道（和电线），以适应最宽的通道配置。
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公开(公告)号：US20130346665A1
公开(公告)日：2013-12-26
申请号：US13528146
申请日：2012-06-20
IPC分类号： G06F13/20
CPC分类号： G06F13/4018 , G06F9/4411 , G06F13/423
摘要： Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration.
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7.发明申请Method for Creating Data Transfer Packets With Embedded Management Information 审中-公开使用嵌入式管理信息创建数据传输数据包的方法公开(公告)号：US20080313240A1
公开(公告)日：2008-12-18
申请号：US11764310
申请日：2007-06-18
CPC分类号： H04L47/10 , H04L1/1671 , H04L47/35 , H04L47/39 , H04L69/22
摘要： In a method of communicating management information from a completing entity to a requesting entity in a digital communication system, the availability of management information to be sent from the completing entity to the requesting entity is detected when generating a data packet that does not have a primary purpose of transmitting management information. The management information is included in a management information data field and the management information data field is appended to the data packet. The data packet and the management information are transmitted from the completing entity to the requesting entity.
摘要翻译： 在从数字通信系统中的完成实体向请求实体传送管理信息的方法中，当生成不具有主要数据包的数据包时，检测到从完成实体发送到请求实体的管理信息的可用性 传送管理信息的目的。 管理信息被包括在管理信息数据字段中，并且管理信息数据字段被附加到数据包。 数据包和管理信息从完成实体发送到请求实体。
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公开(公告)号：US08949499B2
公开(公告)日：2015-02-03
申请号：US13528192
申请日：2012-06-20
CPC分类号： G06F13/4081 , G06F13/20
摘要： The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy.
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公开(公告)号：US08706938B2
公开(公告)日：2014-04-22
申请号：US13528224
申请日：2012-06-20
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F11/263 , G06F13/00 , G06F13/1605 , G06F13/36 , G06F2213/0026
摘要： Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
摘要翻译： 用于执行用于调节带宽的操作的方法，电路和系统，所述操作包括在存储器处接收调试数据分组和用于在共享总线上传送的功能数据分组。 然后，该操作通过共享总线将功能数据分组和一个或多个调试数据分组根据调制数据分组的预定比率发送到功能数据分组。 然后，该操作将接收到的调试数据分组中的一个或多个丢弃在存储器处，并维持一个或多个丢弃的调试数据分组的计数。 然后，操作基于计数更新预定义的比例，并且使用更新的预定义比率来发送功能数据分组和一个或多个调试数据分组。
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公开(公告)号：US20130346801A1
公开(公告)日：2013-12-26
申请号：US13528224
申请日：2012-06-20
IPC分类号： G06F11/28
CPC分类号： G06F11/263 , G06F13/00 , G06F13/1605 , G06F13/36 , G06F2213/0026
摘要： Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
摘要翻译： 用于执行用于调节带宽的操作的方法，电路和系统，所述操作包括在存储器处接收调试数据分组和用于在共享总线上传送的功能数据分组。 然后，该操作通过共享总线将功能数据分组和一个或多个调试数据分组根据调制数据分组的预定比率发送到功能数据分组。 然后，该操作将接收到的调试数据分组中的一个或多个丢弃在存储器处，并维持一个或多个丢弃的调试数据分组的计数。 然后，操作基于计数更新预定义的比例，并且使用更新的预定义比率来发送功能数据分组和一个或多个调试数据分组。
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